Datasheet > EP1K50

EP1K50

更新时间： 2024-01-14 07:07:08

品牌	Logo	应用领域
阿尔特拉 - ALTERA		PC
页数	文件大小	规格书
34页	456K
描述
1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

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EP1K50 数据手册

1. Enhanced Configuration Devices

(EPC4, EPC8, and EPC16) Data Sheet

CF52002-2.8

Features

This chapter describes the EPC4, EPC8, and EPC16 enhanced configuration devices

(EPC).

■

Single-chip configuration solution for Altera^®ACEX^®1K, APEX^™20K (including

APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria^®GX, Cyclone^®, Cyclone

II, FLEX^®10K (including FLEX 10KE and FLEX 10KA), Mercury^™, Stratix^®II, and

Stratix II GX devices

■

Contains 4-, 8-, and 16-Mbit flash memories for configuration data storage

■

On-chip decompression feature almost doubles the effective configuration

density

■

Standard flash die and a controller die combined into single stacked chip package

External flash interface supports parallel programming of flash and external

processor access to unused portions of memory

■

Flash memory block/sector protection capability via external flash interface

Supported in EPC16 and EPC4 devices

■

Page mode support for remote and local reconfiguration with up to eight

configurations for the entire system

■

Compatible with Stratix series Remote System Configuration feature

Supports byte-wide configuration mode fast passive parallel (FPP); 8-bit data

output per DCLKcycle

■

Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs

Pin-selectable 2-ms or 100-ms power-on reset (POR) time

Configuration clock supports programmable input source and frequency synthesis

■

Multiple configuration clock sources supported (internal oscillator and

external clock input pin)

■

External clock source with frequencies up to 100 MHz

Internal oscillator defaults to 10 MHz; Programmable for higher frequencies of

33, 50, and 66 MHz

■

Clock synthesis supported via user programmable divide counter

■

Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin Ultra

FineLine BGA^®(UFBGA) packages

■

Vertical migration between all devices supported in the 100-pin PQFP package

■

Supply voltage of 3.3 V (core and I/O)

Hardware compliant with IEEE Std. 1532 in-system programmability (ISP)

specification

Configuration Handbook (Complete Two-Volume Set)

12 3 4 5 6 7...34

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与EP1K50相关器件

型号	品牌	获取价格	描述	数据表
EP1K50FC256-1	INTEL	获取价格	Loadable PLD, 0.3ns, CMOS, PBGA256, FINE LINE, BGA-256
EP1K50FC256-1DX	ETC	获取价格	Field Programmable Gate Array (FPGA)
EP1K50FC256-1F	ETC	获取价格	Field Programmable Gate Array (FPGA)
EP1K50FC256-1P	ETC	获取价格	Field Programmable Gate Array (FPGA)
EP1K50FC256-1X	ETC	获取价格	Field Programmable Gate Array (FPGA)
EP1K50FC256-2DX	ETC	获取价格	Field Programmable Gate Array (FPGA)
EP1K50FC256-2F	ETC	获取价格	Field Programmable Gate Array (FPGA)
EP1K50FC256-2N	INTEL	获取价格	Loadable PLD, 0.4ns, CMOS, PBGA256, FINE LINE, BGA-256
EP1K50FC256-2P	ETC	获取价格	Field Programmable Gate Array (FPGA)
EP1K50FC256-2X	ETC	获取价格	Field Programmable Gate Array (FPGA)

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