Datasheet > EP1K10FC484-2

EP1K10FC484-2

更新时间： 2024-01-19 09:17:08

品牌	Logo	应用领域
阿尔特拉 - ALTERA		/
页数	文件大小	规格书
88页	1488K
描述
Loadable PLD, 9.5ns, CMOS, PBGA484, 23 X 23 MM, 1 MM PITCH, FINE LINE, BGA-484

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

EP1K10FC484-2 技术参数

是否Rohs认证：	不符合	生命周期：	Active
Reach Compliance Code：	compliant	风险等级：	5.62
JESD-30 代码：	S-PBGA-B484	JESD-609代码：	e0
湿度敏感等级：	3	输入次数：	136
逻辑单元数量：	576	输出次数：	136
端子数量：	484	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA484,22X22,40
封装形状：	SQUARE	封装形式：	GRID ARRAY
电源：	2.5,2.5/3.3 V	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	子类别：	Field Programmable Gate Arrays
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	Base Number Matches：	1

EP1K10FC484-2 数据手册

ACEX 1K

Programmable Logic Family

April 2000, ver. 1.01

Data Sheet

■

Programmable logic devices (PLDs), providing low cost

system-on-a-programmable-chip integration in a single device

Features...

–

Enhanced embedded array for implementing megafunctions

such as efficient memory and specialized logic functions

Dual-port capability with up to 16-bit width per embedded array

block (EAB)

Preliminary

Information

Logic array for general logic functions

■

High density

–

10,000 to 100,000 typical gates (see Table 1)

Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be

used without reducing logic capacity)

Cost-efficient programmable architecture for high-volume

applications

–

Die size reductions via hybrid process

Low cost solution for high-performance communications

applications

■

System-level features

–

MultiVolt^TMI/O pins can drive or be driven by 2.5-V, 3.3-V, or

5.0-V devices

–

Low power consumption

Bidirectional I/O performance (setup time [t ] and clock-to-

output delay [t ]) up to 250 MHz

–

Fully compliant with the peripheral component interconnect

Special Interest Group (PCI SIG) PCI Local Bus Specification,

Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz

Table 1. ACEX^TM1K Device Features

Feature

EP1K10

EP1K30

EP1K50

EP1K100

Typical gates

10,000

56,000

576

30,000

119,000

1,728

50,000

199,000

2,880

100,000

257,000

4,992

Maximum system gates

Logic elements (LEs)

EABs

Total RAM bits

12,288

130

24,576

171

40,960

249

49,152

333

Maximum user I/O pins

Altera Corporation

A-DS-ACEX-01.01

12 3 4 5 6 7...88

下载PDF

与EP1K10FC484-2相关器件

型号	品牌	描述	获取价格	数据表
EP1K10FI256-2N	INTEL	Loadable PLD, 0.5ns, CMOS, PBGA256, FINE LINE, BGA-256	获取价格
EP1K10FI256-2N	ALTERA	Loadable PLD, 0.5ns, CMOS, PBGA256, FINE LINE, BGA-256	获取价格
EP1K10QC208-2N	INTEL	Loadable PLD, 0.5ns, CMOS, PQFP208, PLASTIC, QFP-208	获取价格
EP1K10QC208-3	INTEL	Loadable PLD, 0.7ns, CMOS, PQFP208, PLASTIC, QFP-208	获取价格
EP1K10TC100-1N	ALTERA	Loadable PLD, 0.4ns, CMOS, PQFP100, TQFP-100	获取价格
EP1K10TC100-3N	ALTERA	Loadable PLD, 0.7ns, CMOS, PQFP100, TQFP-100	获取价格