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EP1K10TC144-2N PDF预览

EP1K10TC144-2N

更新时间: 2024-02-04 18:09:05
品牌 Logo 应用领域
阿尔特拉 - ALTERA 可编程逻辑器件
页数 文件大小 规格书
86页 1204K
描述
Programmable Logic Device Family

EP1K10TC144-2N 数据手册

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ACEX 1K  
Programmable Logic Device Family  
®
May 2003, ver. 3.4  
Data Sheet  
Programmable logic devices (PLDs), providing low cost  
system-on-a-programmable-chip (SOPC) integration in a single  
device  
Features...  
Enhanced embedded array for implementing megafunctions  
such as efficient memory and specialized logic functions  
Dual-port capability with up to 16-bit width per embedded array  
block (EAB)  
Logic array for general logic functions  
High density  
10,000 to 100,000 typical gates (see Table 1)  
Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be  
used without reducing logic capacity)  
Cost-efficient programmable architecture for high-volume  
applications  
13  
Cost-optimized process  
Low cost solution for high-performance communications  
applications  
System-level features  
MultiVoltTM I/ O pins can drive or be driven by 2.5-V, 3.3-V, or  
5.0-V devices  
Low power consumption  
Bidirectional I/ O performance (setup time [tSU] and clock-to-  
output delay [tCO]) up to 250 MHz  
Fully compliant with the peripheral component interconnect  
Special Interest Group (PCI SIG) PCI Local Bus Specification,  
Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz  
Extended temperature range  
Table 1. ACEXTM 1K Device Features  
Feature  
EP1K10  
EP1K30  
EP1K50  
EP1K100  
Typical gates  
10,000  
56,000  
576  
30,000  
119,000  
1,728  
6
50,000  
199,000  
2,880  
10  
100,000  
257,000  
4,992  
12  
Maximum system gates  
Logic elements (LEs)  
EABs  
3
Total RAM bits  
12,288  
136  
24,576  
171  
40,960  
249  
49,152  
333  
Maximum user I/O pins  
Altera Corporation  
1
DS-ACEX-3.4  

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