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EM6325DX-1.7 PDF预览

EM6325DX-1.7

更新时间: 2022-12-15 00:09:30
品牌 Logo 应用领域
EMMICRO 复位电路
页数 文件大小 规格书
8页 230K
描述
Reset Circuit with Manual Reset

EM6325DX-1.7 数据手册

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EM MICROELECTRONIC - MARIN SA  
EM6325  
Reset Circuit with Manual Reset  
Description  
Features  
The EM6325 is an ultra-low current reset circuit available in a  
large variety of configurations and very small packages for  
maximum flexibility in all end-applications up to 125°C and  
using power supplies between 1.5V and 5.5V.  
This circuit monitors the supply voltage of any electronic  
system, and generates the appropriate reset signal after a  
fixed reset timeout period. The threshold defines the  
minimum allowed voltage which guarantees the good  
functionality of the system. When VDD rises above VTH, the  
output remains active for an additional delay time. This  
allows the system to stabilize before getting fully active.  
This circuit features a Manual Reset: an input that asserts  
‰
Manual reset function  
‰
200ms reset timeout period (1.6ms, 25ms, 1600ms on  
request)  
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‰
‰
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Ultra-low supply current of 2.9μA (VDD=3.3V)  
Operating temperature range: -40°C to +125°C  
±1.5% reset threshold accuracy  
11 reset threshold voltages VTH: 4.63V, 4.4V, 3.08V,  
2.93V, 2.63V, 2.2V, 1.8V, 1.66V, 1.57V, 1.38V, 1.31V  
‰
3 reset output options:  
Active-low RESET push-pull  
Active-low RESET open-drain  
reset when pulled low (MR with internal pull-up).  
Small SC70-4L, SC70-5L and SOT23-5L packages as well  
as ultra-low supply current of 2.9μA make the EM6325 an  
ideal choice for portable and battery-operated devices.  
Active-high RESET push-pull  
‰
‰
‰
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Immune to short negative VDD transients  
Guaranteed Reset valid down to 0.9V  
Threshold hysteresis: 2.1% of VTH  
Typical Application  
VDD  
Very small SOT23-5L, SC70-5L and SC70-4L  
VDD  
*
VDD  
Applications  
RESET  
RESET  
‰
‰
‰
‰
‰
‰
‰
‰
Computers  
MPU, DSP  
RESET  
EM6325  
RESET  
Servers and workstations  
Modems  
MR  
GND  
GND  
GND  
Wireless communication  
Metering  
* REXT for open-drain version only  
Playstations  
Block Diagram  
PDA , Webpad  
Automotive systems  
VDD  
Oscillator  
Pin Configuration (top view)  
+
RESET  
RESET  
Reset  
Logic  
VDD  
RESET  
1
2
3
5
GND  
VDD  
MR  
Voltage  
push-pull / open-drain  
1
2
4
3
-
Reference  
GND  
RESET  
(RESET)  
RESET  
4
Filter  
MR  
MR  
push-pull  
SOT23-5 / SC70-5  
SC70-4  
top view  
GND  
top view  
Pin Description  
Pin  
Name  
Function  
SOT23-5L / SC70-5L SC70-4L  
Active-low RESET output. RESET remains low for the reset timeout period and  
1
2
RESET  
GND  
then goes high after all reset conditions are deasserted or after MR goes from low  
to high  
Ground  
2
3
1
2
Active-high RESET output. RESET remains high for the reset timeout period and  
RESET  
then goes low after all reset conditions are deasserted or after MR goes from low to  
high  
Manual Reset input with an internal pull-up 15kΩ resistor. Reset remains active as  
4
5
3
4
MR  
VDD  
long as MR is low and for tPOR after MR returns high. MR can be driven with a  
CMOS output or shorted to ground with a switch  
Supply Voltage (5.5V max.)  
1
www.emmicroelectronic.com  
Copyright © 2005, EM Microelectronic-Marin SA  

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