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EL5221CYZ-T13 PDF预览

EL5221CYZ-T13

更新时间: 2024-02-11 22:56:41
品牌 Logo 应用领域
英特矽尔 - INTERSIL 放大器光电二极管
页数 文件大小 规格书
11页 166K
描述
Dual 12MHz Rail-to-Rail Input-Output Buffer

EL5221CYZ-T13 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:MSOP包装说明:TSSOP, TSSOP8,.19
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.33.00.01
风险等级:5.6Is Samacsys:N
放大器类型:BUFFER最大平均偏置电流 (IIB):0.05 µA
标称带宽 (3dB):12 MHz25C 时的最大偏置电流 (IIB):0.05 µA
最大输入失调电压:12000 µVJESD-30 代码:S-PDSO-G8
JESD-609代码:e3长度:3 mm
湿度敏感等级:2负供电电压上限:-9 V
标称负供电电压 (Vsup):-5 V功能数量:2
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP8,.19
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:+-5/15 V
认证状态:Not Qualified座面最大高度:1.1 mm
最小摆率:7 V/us标称压摆率:10 V/us
子类别:Buffer Amplifier最大压摆率:1.5 mA
供电电压上限:9 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3 mmBase Number Matches:1

EL5221CYZ-T13 数据手册

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EL5221  
Unus ed Buffers  
It is recommended that any unused buffer have the input tied  
to the ground plane.  
Driving Capacitive Loads  
The EL5221 can drive a wide range of capacitive loads. As  
load capacitance increases, however, the -3dB bandwidth of  
the device will decrease and the peaking increase. The  
buffers drive 10pF loads in parallel with 10kwith just 1.5dB  
of peaking, and 100pF with 6.4dB of peaking. If less peaking  
is desired in these applications, a small series resistor  
(usually between 5and 50) can be placed in series with  
the output. However, this will obviously reduce the gain  
slightly. Another method of reducing peaking is to add a  
"snubber" circuit at the output. A snubber is a shunt load  
consisting of a resistor in series with a capacitor. Values of  
150and 10nF are typical. The advantage of a snubber is  
that it does not draw any DC load current or reduce the gain  
Power Supply Bypas s ing and Printed Circuit  
Board Layout  
The EL5221 can provide gain at high frequency. As with any  
high frequency device, good printed circuit board layout is  
necessary for optimum performance. Ground plane  
construction is highly recommended, lead lengths should be  
as short as possible, and the power supply pins must be well  
bypassed to reduce the risk of oscillation. For normal single  
supply operation, where the V - pin is connected to ground,  
S
a 0.1µF ceramic capacitor should be placed from V + to pin  
S
to V - pin. A 4.7µF tantalum capacitor should then be  
S
connected in parallel, placed in the region of the buffer. One  
4.7µF capacitor may be used for multiple devices. This same  
capacitor combination should be placed at each supply pin  
to ground if split supplies are to be used.  
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
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