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EL2142CS PDF预览

EL2142CS

更新时间: 2024-01-23 20:49:19
品牌 Logo 应用领域
ELANTEC 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管信息通信管理局域网
页数 文件大小 规格书
8页 166K
描述
Differential Line Receiver

EL2142CS 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.42输入特性:DIFFERENTIAL
接口集成电路类型:LINE RECEIVER接口标准:GENERAL PURPOSE
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9022 mm湿度敏感等级:3
标称负供电电压:-5 V功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:+-5 V
认证状态:Not Qualified最大接收延迟:
接收器位数:1座面最大高度:1.7272 mm
子类别:Line Driver or Receivers最大压摆率:14 mA
最大供电电压:6.3 V最小供电电压:3 V
标称供电电压:5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3.9116 mmBase Number Matches:1

EL2142CS 数据手册

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EL2142C  
Differential Line Receiver  
Applications Information  
2142-8  
Gain Equation  
e
e
a
c
c
a
(V -V V ) when R1 tied to GND  
IN INB REF  
V
OUT  
((R2 R1)/R1)  
a
((R2 R1)/R1)  
V
(V -V ) when R1 tied to V  
IN INB  
OUT  
REF  
Choice of Feedback Resistor  
For a gain of one, V may be shorted back to  
Capacitance Considerations  
As with many high bandwidth amplifiers, the  
EL2142C prefers not to drive highly capacitive  
OUT  
V
FB  
, but 100X200X improves the bandwidth.  
For gains greater than one, there is little to be  
gained from choosing resistor R1 value below  
200X, for it would only result in increased power  
dissipation and potential signal distortion. Above  
200X, the bandwidth response will develop some  
peaking (for a gain of one), but substantially  
higher R1 values may be used for higher voltage  
gains, such as up to 1 kX at a gain of four before  
peaking will develop.  
loads. It is best if the capacitance on V  
is  
OUT  
kept below 10 pF if the user does not want gain  
peaking to develop. The V node forms a poten-  
FB  
tial pole in the feedback loop, so capacitance  
should be minimized on this node for maximum  
bandwidth.  
The amount of capacitance tolerated on any of  
these nodes in an actual application will also be  
dependent on the gain setting and the resistor  
values in the feedback network.  
5

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