Datasheet > EFM32GG230F512G-E-QFN64

EFM32GG230F512G-E-QFN64

更新时间： 2024-02-10 22:11:26

品牌	Logo	应用领域
芯科 - SILICON		微控制器
页数	文件大小	规格书
72页	1626K
描述
RISC Microcontroller, CMOS

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EFM32GG230F512G-E-QFN64 技术参数

是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	compliant	HTS代码：	8542.31.00.01
风险等级：	1.7	Samacsys Description：	ARM Microcontrollers - MCU 512k Flash, 128k RAM, AES
Base Number Matches：	1

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...the world's most energy friendly microcontrollers

2.1.3 Memory System Controller (MSC)

The Memory System Controller (MSC) is the program memory unit of the EFM32GG microcontroller.

The flash memory is readable and writable from both the Cortex-M3 and DMA. The flash memory is

divided into two blocks; the main block and the information block. Program code is normally written to

the main block. Additionally, the information block is available for special user data and flash lock bits.

There is also a read-only page in the information block containing system and device calibration data.

Read and write operations are supported in the energy modes EM0 and EM1.

2.1.4 Direct Memory Access Controller (DMA)

The Direct Memory Access (DMA) controller performs memory operations independently of the CPU.

This has the benefit of reducing the energy consumption and the workload of the CPU, and enables

the system to stay in low energy modes when moving for instance data from the USART to RAM or

from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMA

controller licensed from ARM.

2.1.5 Reset Management Unit (RMU)

The RMU is responsible for handling the reset functionality of the EFM32GG.

2.1.6 Energy Management Unit (EMU)

The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32GG microcon-

trollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU

can also be used to turn off the power to unused SRAM blocks.

2.1.7 Clock Management Unit (CMU)

The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the

EFM32GG. The CMU provides the capability to turn on and off the clock on an individual basis to all

peripheral modules in addition to enable/disable and configure the available oscillators. The high degree

of flexibility enables software to minimize energy consumption in any specific application by not wasting

power on peripherals and oscillators that are inactive.

2.1.8 Watchdog (WDOG)

The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase appli-

cation reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a

software failure.

2.1.9 Peripheral Reflex System (PRS)

The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module

communicate directly with each other without involving the CPU. Peripheral modules which send out

Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which

apply actions depending on the data received. The format for the Reflex signals is not given, but edge

triggers and other functionality can be applied by the PRS.

2.1.10 Inter-Integrated Circuit Interface (I2C)

The I²C module provides an interface between the MCU and a serial I²C-bus. It is capable of acting as

both a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fast-

mode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s.

Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system.

The interface provided to software by the I²C module, allows both fine-grained control of the transmission

www.silabs.com

2016-03-21 - EFM32GG230FXX - d0035_Rev1.40

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与EFM32GG230F512G-E-QFN64相关器件

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EFM32GG232F512G-E-QFP64	SILICON	获取价格	High Performance 32-bit processor
EFM32GG232F512-QFP64	SILICON	获取价格	EFM32GG232F512-QFP64 是基于 ARM Cortex-M3 的微控制器
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