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EDI8G322048C20MMC PDF预览

EDI8G322048C20MMC

更新时间: 2024-09-27 23:50:11
品牌 Logo 应用领域
其他 - ETC 静态存储器
页数 文件大小 规格书
6页 182K
描述
x32 SRAM Module

EDI8G322048C20MMC 数据手册

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EDI8G322048C  
2048K x 32 Static RAM CMOS, High Speed Module  
FEATURES  
DESCRIPTION  
•2048K x 32 bit CMOS Static  
•Random Access Memory  
The EDI8G322048C is a high speed 64 megabit Static RAM  
module organized as 2048K words by 32 bits. This module is  
constructed from sixteen 1024K x 4 Static RAMs in SOJ pack-  
ages on an epoxy laminate (FR4) board.  
• Access Times: 20, 25, and 35ns  
• Individual Byte Selects  
Four chip enables (EØ-E3) and the highest order address line are  
used to independently enable the four bytes as well as the low  
or high block of addressable memory space. Reading or writing  
can be executed on individual bytes or any combination of  
multiple bytes through proper use of selects.  
• Fully Static, No Clocks  
• TTL Compatible I/O  
•High Density Package  
• 72 lead SIMM, No. 356 (Straight)  
• Common Data Inputs and Outputs  
•Single +5V (±10%) Supply Operation  
The EDI8G322048C is offered in a 72 lead SIMM package, which  
enables 64 megabits of memory to be placed in less than 1.3  
square inches of board space.  
All inputs and outputs are TTL compatible and operate from a  
single 5V supply. Fully asynchronous circuitry requires no clocks  
or refreshing for operation and provides equal access and cycle  
times for ease of use.  
Pins PD1- PD4, are used to identify module memory density in  
applications where alternate modules can be interchanged.  
PIN CONFIGURATION  
PIN NAMES  
AØ-A20  
EØ-E3  
W
Address Inputs  
Chip Enables  
Write Enable  
Output Enable  
Common Data  
Input/Output  
G
DQØ-DQ31  
VCC  
VSS  
NC  
Power (+5V±10%)  
Ground  
No Connection  
8G322048C Pin Config.  
June 2001 Rev. 1  
ECO #14323  
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com  
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