Datasheet > EBD21RD4ADNA

EBD21RD4ADNA

更新时间： 2022-11-26 13:42:33

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
19页	175K
描述
2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks)

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数据手册

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EBD21RD4ADNA 数据手册

EBD21RD4ADNA

Pin Description

Pin name

Function

Address input

Row address

A0 to A12

Column address

A0 to A9, A11, A12

BA0, BA1

Bank select address

Data input/output

DQ0 to DQ63

CB0 to CB7

Check bit (Data input/output)

Row address strobe command

Column address strobe command

Write enable

/RAS

/CAS

/WE

/CS0, /CS1

Chip select

CKE0, CKE1

Clock enable

CK0

Clock input

/CK0

Differential clock input

Input and output data strobe

Clock input for serial PD

Data input/output for serial PD

Serial address input

DQS0 to DQS8

DM0 to DM8/DQS9 to DQS17

SCL

SDA

SA0 to SA2

VDD

Power for internal circuit

Power for serial EEPROM

Input reference voltage

Ground

VDDSPD

VREF

VSS

VDDID

/RESET

VDD identification flag

Reset pin (forces register inputs low)

No connection

Preliminary Data Sheet E0433E10 (Ver. 1.0)

1 2 345 6 7...19

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