ACT8945A
Rev 6, 01-Feb-16
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
Reference Bypass. Connect a 0.047μF ceramic capacitor from REFBP to GA. This pin is
discharged to GA in shutdown.
1
REFBP
2
3
4
5
6
7
8
OUT1
GA
Output Feedback Sense for REG1.
Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP12 and GP3
together at a single point as close to the IC as possible.
REG4 output. Capable of delivering up to 320mA of output current. Connect a 3.3µF ceramic
capacitor from OUT4 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.
OUT4
OUT5
INL
REG5 output. Capable of delivering up to 320mA of output current. Connect a 3.3µF ceramic
capacitor from OUT5 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.
Power Input for REG4, REG5, REG6, and REG7. Bypass to GA with a high quality ceramic
capacitor placed as close to the IC as possible.
REG7 output. Capable of delivering up to 320mA of output current. Connect a 3.3µF ceramic
capacitor from OUT7 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.
OUT7
OUT6
REG6 output. Capable of delivering up to 320mA of output current. Connect a 3.3µF ceramic
capacitor from OUT6 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.
Master Enable Input. Drive nPBIN to GA through a 50kΩ resistor to enable the IC, drive nPBIN
directly to GA to assert a manual reset condition. Refer to the nPBIN Multi-Function Input section
for more information. nPBIN is internally pulled up to VSYS through a 35kꢀ resistor.
9
nPBIN
Power Hold Input. Enable input for all regulators. PWRHLD is internally pulled down to GA through
a 500kꢀ resistor. Refer to the Control Sequences section for more information.
10
11
12
PWRHLD
nRSTO
nIRQ
Active Low Reset Output. See the nRSTO Output section for more information.
Open-Drain Interrupt Output. nIRQ is asserted any time an unmasked fault condition exists or a
charger interrupt occurs. See the nIRQ Output section for more information.
Active-Low Open-Drain Push-Button Status Output. nPBSTAT is asserted low whenever the
nPBIN is pushed, and is high-Z otherwise. See the nPBSTAT Output section for more information.
13
nPBSTAT
Power Ground for REG3. Connect GA, GP12, and GP3 together at a single point as close to the
IC as possible.
14
15
16
GP3
SW3
VP3
Switching Node Output for REG3.
Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close to the
IC as possible.
17
18
19
OUT3
Output Feedback Sense for REG3.
PWREN Power Enable Input. Refer to the Control Sequences section for more information.
Low Battery Indicator Output. nLBO is asserted low whenever the voltage at LBI is lower than
nLBO
1.2V, and is high-Z otherwise. See the Precision Voltage Detector section for more information.
Low Battery Input. The input voltage is compared to 1.2V and the output of this comparison drives
nLBO. See the Precision Voltage Detector section for more information.
20
LBI
21
22
ACIN
AC Input Supply Detection. See the Charge Current Programming section for more information.
CHGLEV Charge Current Selection Input. See the Charge Current Programming section for more information.
www.active-semi.com
- 6 -
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
Copyright © 2016 Active-Semi, Inc.
I2CTM is a trademark of NXP.
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