DTC-1 9 3 0 0
LVDT/RVDT-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
The DTC-19300 is a 12- or 14-bit
LVDT (Linear Variable Differential
Transformer)- or RVDT (Rotary
Variable Differential Transformer)-to-
digital converter which also supplies
the AC excitation to drive the LVDT.
Internal AC excitation voltage, fre-
quency, signal gain and resolution are
all programmable for optimum system
performance. Packaged in a 36-pin
hybrid, the DTC-19300 also features
Velocity (VEL) and Built-In-Test (BIT)
outputs. The three-state digital out-
puts are provided in a two byte for-
mat, for easy computer interface.
and is in phase with, the LVDT out-
put signal. Therefore, any errors due
to the transducer’s phase shift are
virtually eliminated. Additionally, the
programmability of the DTC-19300
will accomodate a broad range of
LVDT’s.
• Internal Oscillator:
Programmable for Voltage and
Frequency
• Programmable Signal Gain
• Programmable for 12- or 14-Bit
Resolution
APPLICATIONS
The DTC-19300 provides many fea-
tures previously supplied by individual
system components. Because of its
internal AC source, programmable
features, fault indicator (BIT), and
velocity output (VEL), the need for
other system circuits is minimized.The
DTC-19300 is an excellent choice for
applications using the LVDT transduc-
er for position feedback, such as mili-
tary, commercial aerospace and
industrial control systems.
• Velocity Output
• Built-In-Test Output
• Three-State, Two-Byte
Digital Output
The DTC-19300 has been designed
precisely for use with an LVDT.
Inherent characteristics of the DTC-
19300, such as the input to output
phase shift, have been given con-
siderable attention. The converter’s
reference voltage is derived from,
PHASE
COMP
10k
R1
10k
C2
R5
35
29
SJ
SO
DTC-19300
18
26
REFERENCE
CONDITIONER
BIT
DETECT
ZERO SET
TIMING
BIT
FULL
VEL
SCALE
LVDT
R2
SG
34
-
PROG
GAIN
AMP
DIFF
SIG
HIGH
ACCURACY
RATIO BRIDGE
ERROR
PROCESSOR
ERROR
AMP
+
VCO
DEMOD
REF
U
T
1 LSB ANTILITTER
FEEDBACK
33
32
SUM
(REF)
S
R
DIF
GAIN
24
14 BIT BRIDGE
TRANSPARENT
LATCH
e
25
V
U
14 BIT
31 RO
U-D COUNTER
U/D
T
50 ns DELAY
36 RI
23
17
A
INHIBIT
TRANSPARENT
LATCH
14 BIT OUTPUT
TRANSPARENT
LATCH
INH
C1
INH
Q
19 OSC
21
+
30
+5 V
POWER
OSCILLATOR
POWER
SUPPLY
CONDITIONER
27
FREQ
R4
3 STATE
TTL BUFFER
3 STATE
TTL BUFFER
INTERNAL
DC REF (11V)
+15 V
22
RM
20
AMPL
R3
1
16
EL
EM
BITS 1-6
BITS 7-14
FIGURE 1. DTC-19300 BLOCK DIAGRAM
1986, 1999 Data Device Corporation
©