Datasheet > DSS6NC52A220T41B

DSS6NC52A220T41B

更新时间： 2024-02-08 20:52:30

品牌	Logo	应用领域
村田 - MURATA		LTE
页数	文件大小	规格书
62页	472K
描述
Data Line Filter, 1 Function(s), 100V, 6A,

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技术参数
数据手册

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DSS6NC52A220T41B 技术参数

生命周期：	Obsolete	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8504.50.80.00
风险等级：	5.84	其他特性：	BUILT-IN FERRITE BEAD TYPE STRUCTURE; INCRIMP LEAD TYPE
电容：	22 µF	滤波器类型：	DATA LINE FILTER
安装类型：	THROUGH HOLE MOUNT	功能数量：	1
最高工作温度：	85 °C	最低工作温度：	-25 °C
包装方法：	BULK	额定电流：	6 A
额定电压：	100 V	Base Number Matches：	1

DSS6NC52A220T41B 数据手册

MAX 7000

Programmable Logic

Device Family

March 2001, ver. 6.1

Data Sheet

■

High-performance, EEPROM-based programmable logic devices

(PLDs) based on second-generation MAX^®architecture

5.0-V in-system programmability (ISP) through the built-in

IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in

MAX 7000S devices

Features...

–

ISP circuitry compatible with IEEE Std. 1532

■

Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S

devices

Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S

devices with 128 or more macrocells

Complete EPLD family with logic densities ranging from 600 to

5,000 usable gates (see Tables 1 and 2)

5-ns pin-to-pin logic delays with up to 175.4-MHz counter

frequencies (including interconnect)

PCI-compliant devices available

For information on in-system programmable 3.3-V MAX 7000A or 2.5-V

MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family

Data Sheet or the MAX 7000B Programmable Logic Device Family Data

Sheet.

Table 1. MAX 7000 Device Features

Feature

EPM7032

EPM7064

EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E

Usable

600

1,250

1,800

2,500

3,200

3,750

5,000

gates

Macrocells

128

160

192

256

Logic array

blocks

Maximum

100

104

124

164

user I/O pins

(ns)

7.5

(ns)

2.5

FSU

CO1

CNT

(ns)

4.5

125.0

4.5

125.0

(MHz)

151.5

100.0

90.9

Altera Corporation

A-DS-M7000-06.1

12 3 4 5 6 7...62

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