Datasheet > DSP56321VL200

DSP56321VL200

更新时间： 2024-02-23 12:42:25

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		数字信号处理器
页数	文件大小	规格书
84页	1566K
描述
24-Bit Digital Signal Processor

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数据手册

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DSP56321VL200 数据手册

DSP56321

Rev. 11, 2/2005

Freescale Semiconductor

Technical Data

DSP56321

24-Bit Digital Signal Processor

The DSP56321 is intended

for applications requiring a

large amount of internal

memory, such as networking

and wireless infrastructure

applications. The onboard

EFCOP can accelerate

Memory Expansion Area

Program

RAM

Triple

Timer

32 K × 24 bits

SCI

ESSI

HI08

EFCOP

X Data

RAM

Y Data

RAM

31 K × 24 bits

and

Instruction

Cache

1024 × 24 bits

80 K × 24 bits 80 K × 24 bits

Peripheral

general filtering applications,

such as echo-cancellation

applications, correlation, and

general-purpose convolution-

based algorithms.

Expansion Area

YAB

Address

External

Address

Bus

XAB

PAB

DAB

Generation

Unit

Address

Switch

Six Channel

DMA Unit

External

Bus

24-Bit

DSP56300

Core

Interface

and

Bootstrap

ROM

Control

I - Cache

Control

DDB

YDB

XDB

PDB

GDB

What’s New?

Rev. 11 includes the following

changes:

External

Data

Bus

Internal

Data

Bus

Switch

Data

Switch

•

Adds lead-free packaging and

part numbers.

Power

Management

Data ALU

Program

Interrupt

Controller

Program

Decode

Controller

Program

Address

Clock

Generator

→

24 × 24 56 56-bit MAC

Two 56-bit Accumulators

56-bit Barrel Shifter

JTAG

PLL

Generator

OnCE™

EXTAL

XTAL

RESET

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

PINIT/NMI

Figure 1. DSP56321 Block Diagram

The Freescale DSP56321, a member of the DSP56300 DSP family, supports networking, security encryption, and

home entertainment using a high-performance, single-clock-cycle-per- instruction engine (DSP56000 code-

compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller

(see Figure 1).

The DSP56321 offers 275 million multiply- accumulates per second (MMACS) performance, attaining 550

MMACS when the EFCOP is in use. It operates with an internal 275 MHz clock with a 1.6 volt core and

independent 3.3 volt input/output (I/O) power. By operating in parallel with the core, the EFCOP provides overall

enhanced performance and signal quality with no impact on channel throughput or total channel support. This

device is pin-compatible with the Freescale DSP56303, DSP56L307, DSP56309, and DSP56311.

12 3 4 5 6 7...84

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