DSA1101/21/05/25
TABLE 1-1:
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Min.
Typ.
Max.
Units Conditions
Supply Voltage (Note 1)
VDD
2.25
—
3.63
V
—
DSA1101/05, EN pin low. Output
is disabled and device is in
standby
—
—
0.095
Supply Current
IDD
mA
DSA1121/25, EN pin low, output
is disabled
—
—
20
21
22
35
EN pin high, output is enabled
CL = 15 pF, FO = 100 MHz
Frequency Stability
(Including frequency
variations due to initial
tolerance, temp. and
power supply voltage)
—
—
—
—
±20
±25
Δf
ppm All temp ranges
—
—
±50
Aging
Δf
—
—
—
—
±5
5
ppm 1 year @ 25°C
Startup Time (Note 2)
Input Logic Levels
Input Logic High
tSU
ms
T = 25°C
VIH
VIL
tDS
0.75 x VDD
—
—
—
—
V
V
—
Input Logic Low
—
—
0.1 x VDD
—
Output Disable Time (Note 3)
5
5
ns
ms
ns
—
DSA1101/05
DSA1121/25
Output Enable Time
tEN
—
—
—
—
20
Enable Pull-Up Resistor
(Note 4)
40
—
kΩ
Internally pulled-up
CMOS Output
Output Logic Level High
Output Logic Level Low
VOH
VOL
0.9 x VDD
—
—
—
—
V
V
I = ±6 mA
0.1 x VDD
DSA1101/21, 20% to 80%,
CL = 15 pF
—
—
—
1.1
4
2
5
2
Output Transition Rise Time
tR
ns
ns
DSA1105/25, 20% to 80%,
CL = 15 pF
DSA1101/21, 20% to 80%,
CL = 15 pF
1.3
Output Transition Fall Time
Frequency
tF
DSA1105/25, 20% to 80%,
CL = 15 pF
—
4.7
—
6
2.3
3.3
170
170
CL = 15 pF and –40°C to +85°C
fO
MHz
%
CL = 15 pF, –40°C to +105°C
and –40°C to +125°C
—
Output Duty Cycle
Period Jitter
SYM
JPER
45
—
—
—
—
—
3
55
—
—
—
2
—
psRMS FOUT = 125 MHz
200 kHz to 20 MHz @ 125 MHz
0.3
0.38
1.7
Integrated Phase Noise
JPH
psRMS 100 kHz to 20 MHz @ 125 MHz
12 kHz to 20 MHz @ 125 MHz
Note 1: Pin 6 VDD should be filtered with 0.1 µF capacitor.
2: tSU is time to 100 ppm of output frequency after VDD is applied and outputs are enabled.
3: Output Waveform and Test Circuit figures define the parameters.
4: Output is enabled if pad is floated or not connected.
2018 Microchip Technology Inc.
DS20005890B-page 3