DS8908B

更新时间： 2024-02-01 06:07:54

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
11页	197K
描述
DS8908B AM/FM Digital Phase-Locked Loop Frequency Synthesizer

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

DS8908B 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP, DIP20,.3	Reach Compliance Code：	unknown
风险等级：	5.92	解调类型：	AM/FM
JESD-30 代码：	R-PDIP-T20	JESD-609代码：	e0
端子数量：	20	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装等效代码：	DIP20,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
电源：	5 V	认证状态：	Not Qualified
子类别：	Other Consumer ICs	表面贴装：	NO
技术：	BIPOLAR	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
Base Number Matches：	1

DS8908B 数据手册

Timing Diagrams* (Continued)

AM/FM Frequency Synthesizer (Scan Mode)

TL/F/5111–12

*Timing diagrams are not drawn to scale. Scale within any one drawing may not be consistent, and intervals are defined positive as drawn.

SERIAL DATA ENTRY INTO THE DS8908B

These data bits are interpreted as follows:

Data Bit Position

Last

Data Interpretation

Serial information entry into the DS8908B is enabled by a

low level on the ENABLE input. One binary bit is then ac-

cepted from the DATA input with each positive transition of

the CLOCK input. The CLOCK input must be low for the

specified time preceding and following the negative tran-

sition of the ENABLE input.

Bit 19 Output (Pin 2)

Bit 18 Output (Pin 1)

(1)

Ref. Freq. Select Bit 17

2nd to Last

3rd to Last

4th to Last

5th to Last

6th to Last

7th to Last

8th to Last

9th to Last

10th to Last

11th to Last

12th to Last

13th to Last

14th to Last

15th to Last

16th to Last

17th to Last

18th to Last

19th to Last

(1)

Ref. Freq. Select Bit 16

AM/FM Select Bit 15

The first two bits accepted following the negative transition

of the ENABLE input are interpreted as address. If these

address bits are not 1,1 no further information will be ac-

cepted fromt he DATA inputs, and the internal data latches

will not be changed when ENABLE returns high.

)

(2 )

If these first two bits are 1,1, then all succeeding bits are

accepted as data, and are shifted successively into the in-

ternal shift register as long as ENABLE remains low.

(2 )

(2)

Any data bits preceding the 19th to last bit will be shifted

out, and thus are irrelevant. Data bits are counted as any

bits following two valid address bits (1,1) with the ENABLE

low. When the ENABLE input returns high, any further serial

data entry is inhibited. Upon this positive transition, the data

in the internal shift register is transferred into the internal

data latches. Note that until this time, the states of the inter-

nal data latches have remained unchanged.

(2 )

LSB of N(2 )

Note 1: See Reference Frequency Select Truth Table.

Note 2: The actual divide code is N 1, ie., the number loaded plus 1.

Truth Table

Reference Frequency Selection Truth Table

Reference

Frequency

Serial Data

Bit 16

Bit 17

(kHz)

1...3 4 567 8 9...11

下载PDF

与DS8908B相关器件

型号	品牌	描述	获取价格	数据表
DS8908BN	NSC	DS8908B AM/FM Digital Phase-Locked Loop Frequency Synthesizer	获取价格
DS8908J/A+	ETC	AM/FM Receiver Circuit	获取价格
DS8908N	ETC	AM/FM Receiver Circuit	获取价格
DS8908N/A+	ETC	AM/FM Receiver Circuit	获取价格
DS8908N/B+	ETC	AM/FM Receiver Circuit	获取价格
DS8911	NSC	Sound Up-Conversion Frequency Synthesizer	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

DS8908B

DS8908B 技术参数

DS8908B 数据手册

与DS8908B相关器件

与DS8908B相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

DS8908B

DS8908B 技术参数

DS8908B 数据手册

与DS8908B相关器件

与DS8908B相关文章

您还可以找

您在本页遇到什么问题？