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DS64EV100 PDF预览

DS64EV100

更新时间: 2024-02-18 13:56:09
品牌 Logo 应用领域
美国国家半导体 - NSC /
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10页 888K
描述
Programmable Single Equalizer

DS64EV100 数据手册

 浏览型号DS64EV100的Datasheet PDF文件第2页浏览型号DS64EV100的Datasheet PDF文件第3页浏览型号DS64EV100的Datasheet PDF文件第4页浏览型号DS64EV100的Datasheet PDF文件第5页浏览型号DS64EV100的Datasheet PDF文件第6页浏览型号DS64EV100的Datasheet PDF文件第7页 
November 9, 2007  
DS64EV100  
Programmable Single Equalizer  
General Description  
Features  
The DS64EV100 programmable equalizer provides compen-  
sation for transmission medium losses and reduces the medi-  
um-induced deterministic jitter for NRZ data channel. The  
DS64EV100 is optimized for operation up to 10 Gbps for both  
cables and FR4 traces. The equalizer channel has eight lev-  
els of input equalization that can be programmed by three  
control pins.  
Equalizes up to 24 dB loss at 10 Gbps  
Equalizes up to 22 dB loss at 6.4 Gbps  
8 levels of programmable equalization  
Operates up to 10 Gbps with 30” FR4 traces  
Operates up to 6.4 Gbps with 40” FR4 traces  
0.175 UI residual deterministic jitter at 6.4 Gbps with 40”  
FR4 traces  
The equalizer supports both AC and DC-coupled data paths  
for long run length data patterns such as PRBS-31, and bal-  
anced codes such as 8b/10b. The device uses differential  
current-mode logic (CML) inputs and outputs, and is available  
in a 3 mm x 4 mm 14-pin leadless LLP package. Power is  
supplied from either a 2.5V or 3.3V supply.  
Single 2.5V or 3.3V power supply  
Supports AC or DC-Coupling with wide input common-  
mode  
Low power consumption: 100 mW Typ at 2.5V  
Small 3 mm x 4 mm 14-pin LLP package  
>8 kV HBM ESD  
-40 to 85°C operating temperature range  
Simplified Application Diagram  
20196401  
© 2007 National Semiconductor Corporation  
201964  
www.national.com  

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