DS4000 Digitally Controlled TCXO
AC ELECTRICAL CHARACTERISTICS—2-WIRE SERIAL INTERFACE
(VCC = 4.75 to 5.25V, TA = -40LC to +85LC)
PARAMETER
SYMBOL
CONDITION
Fast mode
MIN
0
TYP
MAX
400
UNITS
SCL Clock Frequency
fSCL
kHz
Standard mode
Fast mode
0
100
1.3
Bus Free Time Between
a STOP and START
Condition
tBUF
ꢀs
Standard mode
4.7
Fast mode (Note 7)
Standard mode (Note 7)
Fast mode
0.6
4.0
1.3
Hold Time (Repeated)
START Condition
tHD:STA
ꢀs
ꢀs
Low Period of SCL
Clock
tLOW
Standard mode
4.7
Fast mode
0.6
4.0
0.6
High Period of SCL
Clock
tHIGH
ꢀs
Standard mode
Fast mode
Setup Time for a
Repeated START
Condition
tSU:STA
tHD:DAT
tSU:DAT
ꢀs
ꢀs
ns
Standard mode
4.7
Fast mode (Note 8)
0
0
0.9
0.9
Data Hold Time
Data Setup Time
Standard mode (Note 8)
Fast mode (Note 9)
100
250
Standard mode (Note 9)
Fast mode (Note 9)
Standard mode (Note 9)
Fast mode (Note 10)
Standard mode (Note 10)
Fast mode
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
0.6
300
1000
300
Rise Time of Both SDA
and SCL
ns
ns
ꢀs
tR
Fall Time of Both SDA
and SCL
tF
1000
Setup Time for STOP
Condition
tSU:STO
Standard mode
4.0
Capacitive Load for
Each Bus Line
(Note 10)
400
pF
pF
CB
CI
Input Capacitance
5
Note 7: After this period, the first clock pulse is generated.
Note 8: The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 9: A fast-mode device can be used in a standard mode system, but the requirement t
>250ns must then be met. This is automatically
SU:DAT
the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL
signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT (1000 + 250 = 1250ns) before the SCL line is released.
Note 10: CB: Total capacitance of one bus line in pF.
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