Datasheet > DS2405/TR

DS2405/TR

更新时间： 2024-02-08 02:18:23

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
15页	236K
描述
Peripheral IC

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DS2405/TR 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	SOT-223	包装说明：	SOP, SOT-223
针数：	4	Reach Compliance Code：	compliant
HTS代码：	8542.32.00.71	风险等级：	5.62
JESD-30 代码：	R-PDSO-G4	JESD-609代码：	e3
长度：	6.5 mm	内存密度：	64 bit
内存集成电路类型：	MEMORY CIRCUIT	内存宽度：	1
湿度敏感等级：	1	功能数量：	1
端子数量：	4	字数：	64 words
字数代码：	64	工作模式：	ASYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	64X1	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOT-223
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	电源：	3/5 V
认证状态：	Not Qualified	座面最大高度：	1.8 mm
子类别：	SRAMs	最大供电电压 (Vsup)：	6 V
最小供电电压 (Vsup)：	2.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	2.3 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	3.5 mm
Base Number Matches：	1

DS2405/TR 数据手册

DS2405

3. The master reads 1 bit from the 1-Wire bus. Each device will respond by placing the value of the first

bit of its respective ROM data onto the 1-Wire bus. Devices 1 and 4 will place a 0 onto the 1-Wire

bus; that is, they pull it low. Devices 2 and 3 will send a 1 by allowing the line to stay high. The result

is the logical AND of all devices on the line; therefore the master reads a 0. The master will issue

another read time slot. Since the ROM Search command is being executed, all devices respond to this

second read by placing the complement of the first bit of their respective ROM data onto the 1-Wire

Bus. Devices 1 and 4 will send a 1; devices 2 and 3 will send a 0. Thus the 1-Wire bus will be pulled

low. The master again reads a 0 for the complement of the first ROM data bit. This tells the master

that there are devices on the bus that have a 0 in the first position and others that have a 1. If all

devices had a 0 in this bit position, the reading would be 01; if the bit position contained a 1, the result

would be 10. (Note that the 11 condition indicates that no devices are present on the 1-Wire bus.)

4. The master now decides to write a 0 on the 1-Wire bus. This deselects Devices 2 and 3 for the

remainder of the search pass, leaving only devices 1 and 4 participating in the search process.

5. The master performs two more reads and receives a 0 followed by a 1 bit. This indicates that all active

devices have a 0 in this bit position of their ROM.

6. The master then writes a 0 to keep devices 1 and 4 selected.

7. The master executes two reads and receives two 0 bits. This again indicates that both 1 and 0 exist as

the third bit of the ROM of the active devices.

8. The master again writes a 0. This deselects device 1, leaving device 4 as the only active device.

9. Subsequent reads to the end of the ROM will not show bit conflicts. Therefore, they directly tell the

master the ROM contents of the active device. After having learned any new ROM bit, the master has

to resend this bit to keep the device selected. As soon as all ROM bits of the device are known and the

last bit is resent by the master, the device is ready to output the state of the PIO pin using additional

read time slots.

10. The master must learn the other devices’ ROM data. Therefore, it starts another ROM Search

sequence by repeating steps 1 through 7.

11. At the highest bit position, where the master wrote a 0 at the first pass (step 8), it now writes a 1. This

deselects device 4, leaving device 1 active.

12. As in step 9, subsequent reads to the end of the ROM will not show bit conflicts. This completes the

second ROM Search pass where the master has learned another ROM’s contents.

13. The master must learn the other devices’ ROM data. Therefore, it starts another ROM Search

sequence by repeating steps 1 to 3.

14. At the second highest bit position where the master wrote a 0 at the first pass (step 4), it now writes a

1. This deselects devices 1 and 4, leaving devices 2 and 3 active.

15. The master sends two read time slots and receives two 0 bits, indicating a bit conflict.

16. The master again decides to write a 0. This deselects device 3, leaving device 2 as the only active

device.

17. As in step 9, subsequent reads to the end of the ROM will not show bit conflicts. This completes the

third ROM Search pass where the master has learned another ROM’s contents.

6 of 15

1...3 4 567 8 9...15

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与DS2405/TR相关器件

型号	品牌	描述	获取价格	数据表
DS2405_07	DALLAS	Addressable Switch	获取价格
DS2405+	MAXIM	Memory Circuit, 64X1, CMOS, PBCY3, ROHS COMPLIANT, TO-92, 3 PIN	获取价格
DS2405P	DALLAS	Addressable Switch	获取价格
DS2405P/R	DALLAS	Addressable Switch	获取价格
DS2405P/T	DALLAS	Addressable Switch	获取价格
DS2405P/T&R	MAXIM	Memory Circuit, 64X1, CMOS, PDSO6, 3.70 X 4 MM, 1.50 MM HEIGHT, TSOC-6	获取价格

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