Fast Sample-and-Hold Circuit
DS1843
DS1843
INPUT MODEL
CURRENT
MIRROR OUTPUT
R
R
SW
SW
V
V
INP
INN
C
C
C
C
C
IN
IN
S
S
PAR
R
IN
Figure 1. Input Impedances for Settling Time Calculations Diagram
Figure 1 shows the simplified diagram of input imped-
ances for settling time calculations. Sample time is
divided into two parts:
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS1843,
1) t : Internal settling time (max 250ns). During this
IST
decouple the power-supply pin, V , with a 0.01µF or
CC
time, voltage V (V
stant of:
- V
) rises with a time con-
INN
IN INP
0.1µF capacitor. Use a high-quality X7R or equivalent
ceramic surface-mount capacitor.
R
IN
x (C + C
)
PAR
IN
DS1843 Estimated Settling Time
The settling time is dependent on the gain ratio of the
current mirror used at the input of the DS1843. For
example, the MAX4007 includes a 10:1 ratio current
mirror. This requires a 5kΩ resistor to create a 1V full-
scale output with 2mA current input to the MAX4007.
This resistor can be decreased to 2.5kΩ by using the
DS1842, which has a 5:1 ratio current mirror.
2) t : During this period two things happen:
RC
a. Input V keeps increasing from its value at t
IN
to its final value with a new time constant of:
IST
2
2
⎧
⎨
⎩
⎫
⎬
⎭
R
× C + C
+ R
(
× C
SW S
(
)
)
(
)
IN
IN
PAR
b. R
and C track this V (input) with a time con-
SW
SW
stant of R
S IN
x C , which is 12.5ns (worst case).
S
Variable Definitions:
Example:
R : Input resistor. The current mirror creates a voltage
IN
across this resistor.
Approximate accuracy calculations can be done for an
input voltage based on the above impedance values.
These calculations can be divided into three parts.
R
: Resistance of series switch that connects internal
SW
circuitry to input pins after t
time.
IST
1) Accuracy of input at t
(250ns):
IST
C : 7pF parasitic (ESD) capacitor.
IN
C
: External parasitic capacitance. A current mirror's
−t
PAR
1
output and typical trace capacitance are less than
10pF.
⎡
⎤
R
× C +C
(
)
IN
IN
PAR
⎣
⎦
Accuracy = 1− e
C : 5pF sample capacitor.
S
where t = t
= 250ns.
1
IST
t
: Internal settling time based on t from the AC elec-
S
IST
At t
the internal circuit tags input impedance.
IST
trical specification. The minimum t includes one time
S
This causes charge redistribution to occur, which
causes a dip in the input voltage. The worst-case
constant. t
removes this time constant.
IST
value of the input voltage at t
IST
is:
t
: RC settling time of the input.
RC
−t
⎡
⎤
⎥
⎥
⎥
IST
⎡
⎤
⎢
C
⎡
⎤
R
× C +C
(
)
S
IN
IN
PAR
⎣
⎦
V
= ⎢1−
⎥ × 1− e
× V
IN
⎢
IN@t
IST
C
+ C
+ C
PAR S
⎢
⎣
(
)
⎥
⎢
IN
⎦
⎢
⎥
⎣
⎦
_______________________________________________________________________________________
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