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DS1726U/TR PDF预览

DS1726U/TR

更新时间: 2024-01-12 05:41:35
品牌 Logo 应用领域
达拉斯 - DALLAS /
页数 文件大小 规格书
13页 217K
描述
Sensor/Transducer, 8 Pin, Plastic/epoxy,

DS1726U/TR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:TSSOP8,.19Reach Compliance Code:unknown
风险等级:5.87安装特点:SURFACE MOUNT
端子数量:8最大工作电流:1.25 mA
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装等效代码:TSSOP8,.19
封装形状/形式:RECTANGULAR电源:3/5 V
子类别:Other Sensors表面贴装:YES
Base Number Matches:1

DS1726U/TR 数据手册

 浏览型号DS1726U/TR的Datasheet PDF文件第1页浏览型号DS1726U/TR的Datasheet PDF文件第2页浏览型号DS1726U/TR的Datasheet PDF文件第3页浏览型号DS1726U/TR的Datasheet PDF文件第5页浏览型号DS1726U/TR的Datasheet PDF文件第6页浏览型号DS1726U/TR的Datasheet PDF文件第7页 
DS1626/DS1726  
EEPROM AC ELECTRICAL CHARACTERISTICS  
(VDD = 2.7V to 5.5V; TA = -55°C to +125°C.)  
PARAMETER  
EEPROM Write Cycle Time  
EEPROM Writes  
SYMBOL CONDITIONS  
MIN  
TYP  
MAX UNITS  
twr  
4
10  
ms  
Writes  
Years  
NEEWR  
tEEDR  
-55°C to +55°C  
-55°C to +55°C  
50k  
10  
EEPROM Data Retention  
AC ELECTRICAL CHARACTERISTICS  
(VDD = 2.7V to 5.5V; TA = -55°C to +125°C.)  
PARAMETER  
SYMBOL CONDITIONS  
MIN  
TYP  
MAX UNITS  
9-bit  
93.75  
10-bit  
11-bit  
187.5  
Temperature Conversion Time  
tTC  
ms  
375  
12-bit  
750  
ns  
Data In to Clock Setup  
Clock to Data In Hold  
Clock to Data Out Delay  
Clock Low/High Time  
Clock Frequency  
tDC  
tCDH  
tCDD  
tCL, tCH  
fCLK  
tR, tF  
tRC  
(Note 5)  
(Note 5)  
(Notes 5, 6)  
(Note 5)  
(Note 5)  
(Note 5)  
(Note 5)  
(Note 5)  
(Note 7)  
(Note 5)  
(Note 5)  
(Note 8)  
35  
40  
ns  
ns  
ns  
150  
285  
0
1.75  
500  
MHz  
ns  
Clock Rise/Fall Time  
RST to Clock Setup  
Clock to RST Hold  
RST Inactive Time  
Clock High to I/O Hi-Z  
RST Low to I/O Hi-Z  
CNV Pulse Width  
100  
40  
125  
ns  
tCRH  
tRI  
ns  
ns  
tCDZ  
tRDZ  
tCNV  
CI/O  
CI  
50  
50  
500ms  
ns  
ns  
250ns  
I/O Capacitance  
Input Capacitance  
10  
5
pF  
pF  
NOTES:  
1) All voltages are referenced to ground.  
2) See Figure 2 for TYPICAL OPERATING CURVES.  
3) ISTBY, IDD specified with DQ, CLK/CNV = VDD and RST = GND.  
4) Drift data is based on a 1000hr stress test at +125°C with VDD = 5.5V.  
5) See Timing Diagrams in Figure 3. All timing is referenced to 0.7 x VDD and 0.3 x VDD.  
6) Load capacitance = 50pF.  
7) tRI must be 10ms minimum following any write command that involves the E2 memory.  
8) 250ns is the guaranteed minimum pulse width for a conversion to start, however, a smaller pulse  
width may start a conversion.  
4 of 13  

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