Pin Descriptions
Pin
Name
TQFP Pin
Number
LLP Pin
Number
I/O, Type
Description
DIFFERENTIAL INPUTS
IN0+
IN0−
13
14
9
10
I, LVDS
I, LVDS
I, LVDS
I, LVDS
Channel 0 inverting and non-inverting differential inputs.
Channel 1 inverting and non-inverting differential inputs.
Channel 2 inverting and non-inverting differential inputs.
Channel 3 inverting and non-inverting differential inputs.
IN1+
IN1−
15
16
11
12
IN2+
IN2−
19
20
13
14
IN3+
IN3−
21
22
15
16
DIFFERENTIAL OUTPUTS
OUT0+
OUT0−
48
47
32
31
O, LVDS Channel 0 inverting and non-inverting differential outputs. (Note 2)
O, LVDS Channel 1 inverting and non-inverting differential outputs. (Note 2)
O, LVDS Channel 2 inverting and non-inverting differential outputs. (Note 2)
O, LVDS Channel 3 inverting and non-inverting differential outputs. (Note 2)
OUT1+
OUT1−
46
45
30
29
OUT2+
OUT2−
42
41
28
27
OUT3+
OUT3-
40
39
26
25
DIGITAL CONTROL INTERFACE
PWDN
PEM
12
2
8
2
I, LVTTL A logic low at PWDN activates the hardware power down mode (all channels).
I, LVTTL Pre-emphasis Control Input (affects all Channels)
POWER
VDD
3, 4, 5, 7, 10, 11, 3, 4, 6, 7, 20, I, Power VDD = 3.3V, ±10%
28, 29, 32, 33 21
GND
N/C
8, 9, 17, 18, 23, 5 (Note 1)
24, 37, 38, 43,
44
I, Ground Ground reference for LVDS and CMOS circuitry. For the LLP package, the DAP
is used as the primary GND connection to the device in addition to the pin
numbers listed. The DAP is the exposed metal contact at the bottom of the
LLP-32 package. It should be connected to the ground plane with at least 4
vias for optimal AC and thermal performance.
1,6, 25, 26, 27,
30, 31, 34, 35, 18,19,22, 23,
36 24
1, 17,
No Connect
Note 1: Note that for the LLP package the GND is connected thru the DAP on the back side of the LLP package in addition to the actual pin numbers listed.
Note 2: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS15BR400 and DS15BR401 are optimized
for point-to-point backplane and cable applications.
3
www.national.com