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DS1307Z/TR PDF预览

DS1307Z/TR

更新时间: 2024-01-14 20:25:51
品牌 Logo 应用领域
美信 - MAXIM 时钟
页数 文件大小 规格书
15页 669K
描述
64 x 8, Serial, I2C Real-Time Clock

DS1307Z/TR 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8473.30.11.80Factory Lead Time:6 weeks
风险等级:0.66Samacsys Confidence:3
Samacsys Status:Released2D Presentation:https://componentsearchengine.com/2D/0T/232132.1.2.png
Schematic Symbol:https://componentsearchengine.com/symbol.php?partID=232132PCB Footprint:https://componentsearchengine.com/footprint.php?partID=232132
3D View:https://componentsearchengine.com/viewer/3D.php?partID=232132Samacsys PartID:232132
Samacsys Image:https://componentsearchengine.com/Images/9/DS1307ZN+T &R.jpgSamacsys Thumbnail Image:https://componentsearchengine.com/Thumbnails/1/DS1307ZN+T &R.jpg
Samacsys Pin Count:8Samacsys Part Category:Integrated Circuit
Samacsys Package Category:Small Outline PackagesSamacsys Footprint Name:21-0041
Samacsys Released Date:2015-11-27 03:38:06Is Samacsys:N
最大时钟频率:0.032 MHz信息访问方法:I2C
中断能力:NJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.9 mm
湿度敏感等级:1端子数量:8
计时器数量:1最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Timer or RTC最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL最短时间:SECONDS
处于峰值回流温度下的最长时间:NOT SPECIFIED易失性:YES
宽度:3.9 mmuPs/uCs/外围集成电路类型:TIMER, REAL TIME CLOCK
Base Number Matches:1

DS1307Z/TR 数据手册

 浏览型号DS1307Z/TR的Datasheet PDF文件第1页浏览型号DS1307Z/TR的Datasheet PDF文件第2页浏览型号DS1307Z/TR的Datasheet PDF文件第4页浏览型号DS1307Z/TR的Datasheet PDF文件第5页浏览型号DS1307Z/TR的Datasheet PDF文件第6页浏览型号DS1307Z/TR的Datasheet PDF文件第7页 
DS1307 64 x 8, Serial, I2C Real-Time Clock  
AC ELECTRICAL CHARACTERISTICS  
(VCC = 4.5V to 5.5V; TA = 0°C to +70°C, TA = -40°C to +85°C.)  
PARAMETER  
SCL Clock Frequency  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
fSCL  
0
100  
kHz  
Bus Free Time Between a STOP and  
tBUF  
4.7  
4.0  
µs  
µs  
START Condition  
Hold Time (Repeated) START  
Condition  
tHD:STA  
(Note 4)  
LOW Period of SCL Clock  
tLOW  
tHIGH  
4.7  
4.0  
µs  
µs  
HIGH Period of SCL Clock  
Setup Time for a Repeated START  
Condition  
Data Hold Time  
tSU:STA  
4.7  
µs  
tHD:DAT  
tSU:DAT  
0
250  
µs  
ns  
Data Setup Time  
(Notes 5, 6)  
Rise Time of Both SDA and SCL  
Signals  
tR  
1000  
300  
ns  
Fall Time of Both SDA and SCL  
tF  
ns  
Signals  
Setup Time for STOP Condition  
tSU:STO  
4.7  
µs  
CAPACITANCE  
(TA = +25°C)  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX UNITS  
Pin Capacitance (SDA, SCL)  
CI/O  
10  
pF  
pF  
Capacitance Load for Each Bus  
CB  
(Note 7)  
400  
Line  
Note 1:  
Note 2:  
Note 3:  
Note 4:  
Note 5:  
All voltages are referenced to ground.  
Limits at -40°C are guaranteed by design and are not production tested.  
CCS specified with VCC = 5.0V and SDA, SCL = 5.0V.  
After this period, the first clock pulse is generated.  
I
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the  
SCL signal) to bridge the undefined region of the falling edge of SCL.  
Note 6:  
Note 7:  
The maximum tHD:DAT only has to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.  
CB—total capacitance of one bus line in pF.  
3 of 15  

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