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DS1077LU-66.66 PDF预览

DS1077LU-66.66

更新时间: 2024-01-07 16:33:21
品牌 Logo 应用领域
达拉斯 - DALLAS /
页数 文件大小 规格书
20页 277K
描述
Oscillator,

DS1077LU-66.66 技术参数

生命周期:ObsoleteReach Compliance Code:unknown
风险等级:5.84Base Number Matches:1

DS1077LU-66.66 数据手册

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DS1077L  
OVERVIEW  
A block diagram of the DS1077L is shown in Figure 1. The DS1077L consists of four major components:  
1) internal master oscillator, 2) prescalers, 3) programmable divider, and 4) control registers.  
The internal oscillator is factory trimmed to provide a master frequency (master clk) that can be routed  
directly to the outputs (OUT0 & OUT1) or through separate prescalers (P0 & P1). OUT1 can also be  
routed through an additional divider (N).  
The prescaler (P0) divides the master clock by 1, 2, 4, or 8 to be routed directly to the OUT0 pin.  
The prescaler (P1) divides the master clock by 1, 2, 4, or 8 that can be routed to the OUT1 pin or to the  
divider (N) input, which is then routed to the OUT1 pin.  
The programmable divider (N) divides the prescaler output (P1) by any number selected between 2 and  
1025 to provide the main output (OUT1) or it can be bypassed altogether by use of the DIV1 register bit.  
The value of N is stored in the N register.  
The control registers are user-programmable through a 2-wire serial interface to determine operating  
frequency (values of P0, P1, and N) and modes of operation. The register values are stored in EEPROM  
and, therefore, only need to be programmed to alter frequencies and operating modes.  
PIN DESCRIPTIONS  
OUTPUT 1 (OUT1) – This pin is the main oscillator output; its frequency is determined by the control  
register settings for the prescaler P1 (mode bits 1M1 and 1M0) and divider N (DIV WORD).  
OUTPUT 0 (OUT0) – A reference output, OUT0, is taken from the output of the reference-select MUX.  
Its frequency is determined by the control register settings for CTRL0 and values of prescaler P0 (mode  
bits 0M1 and 0M0). (See Table 1.)  
CONTROL PIN 0 (CTRL0) – A multifunctional input pin that can be selected as a MUX select, output  
enable, and/or a power-down. The user-programmable control register values EN0, SEL0, and PDN0  
determine its function. (See Table 1.)  
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