Datasheet > DPA424SN

DPA424SN

更新时间： 2024-01-14 01:17:31

品牌	Logo	应用领域
帕沃英蒂格盛 - POWERINT		转换器电信以太网
页数	文件大小	规格书
34页	2832K
描述
Highly Integrated DC-DC Converter ICs for Power over Ethernet & Telecom Applications

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DPA424SN 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	SFM
包装说明：	,	针数：	6
Reach Compliance Code：	compliant	风险等级：	5.19
模拟集成电路 - 其他类型：	SWITCHING REGULATOR	控制模式：	VOLTAGE-MODE
控制技术：	PULSE WIDTH MODULATION	最大输入电压：	75 V
最小输入电压：	16 V	标称输入电压：	40 V
JESD-30 代码：	R-PSSO-G6	JESD-609代码：	e0
长度：	9.4 mm	功能数量：	1
端子数量：	6	最高工作温度：	125 °C
最低工作温度：	-40 °C	最大输出电流：	1.75 A
封装主体材料：	PLASTIC/EPOXY	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	2.054 mm
表面贴装：	YES	切换器配置：	SINGLE
最大切换频率：	425 kHz	技术：	CMOS
温度等级：	AUTOMOTIVE	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	SINGLE	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	8 mm	Base Number Matches：	1

DPA424SN 数据手册

DPA422-426

overloaded output exists, the feedback loop will close, providing

external CONTROL pin current, before the CONTROL pin

voltage has had a chance to discharge to the lower threshold

voltage of approximately 4.8 V (internal supply undervoltage

lockout threshold). When the externally fed current charges the

CONTROL pin to the shunt regulator voltage of 5.8 V, current in

excess of the consumption of the chip is shunted to SOURCE

through resistor R_Eas shown in Figure 2. This current ﬂowing

through R_Econtrols the duty cycle of the power MOSFET to

provide closed loop regulation. The shunt regulator has a ﬁnite

low output impedance Z_Cthat sets the gain of the error ampliﬁer

when used in a primary feedback conﬁguration. The dynamic

impedance Z_Cof the CONTROL pin together with the external

CONTROL pin capacitance sets the dominant pole for the

control loop.

Oscillator and Switching Frequency

The internal oscillator linearly charges and discharges an

internal capacitance between two voltage levels to create a

sawtooth waveform for the pulse width modulator. The

oscillator sets both the pulse width modulator latch and the

current limit latch at the beginning of each cycle.

The nominal switching frequency of 400 kHz was chosen to

minimize the transformer size and to allow faster power supply

loop response. The FREQUENCY pin, when shorted to the

CONTROL pin, lowers the switching frequency to 300 kHz,

which may be preferable in some applications such as those

employing secondary synchronous rectiﬁcation. Otherwise, the

FREQUENCY pin should be connected to the SOURCE pin for

the default 400 kHz.

Pulse Width Modulator and Maximum Duty Cycle

When a fault condition such as an open loop or overloaded

output prevents the ﬂow of an external current into the CONTROL

pin, the capacitor on the CONTROL pin discharges towards 4.8

V. At 4.8 V auto-restart is activated which turns the output

MOSFET off and puts the control circuitry in a low current

standby mode. The high-voltage current source turns on and

charges the external capacitance again. A hysteretic internal

supply undervoltage comparator keeps V_Cwithin a window of

typically 4.8 V to 5.8 V by turning the high-voltage current

source on and off as shown in Figure 5. The auto-restart circuit

has a divide-by-8 counter that prevents the output MOSFET

from turning on again until eight discharge/charge cycles have

elapsed. This is accomplished by enabling the output MOSFET

only when the divide-by-8 counter reaches full count (S7). The

counter effectively limits DPA-Switch power dissipation as well

as the maximum power delivered to the power supply output by

reducing the auto-restart duty cycle to typically 4%. Auto-

restart mode continues until output voltage regulation is again

achieved through closure of the feedback loop.

The pulse width modulator implements voltage mode control by

driving the output MOSFET with a duty cycle inversely

proportional to the current into the CONTROL pin that is in

excess of the internal supply current of the chip (see Figure 4).

The excess current is the feedback error signal that appears

across R_E(see Figure 2). This signal is ﬁltered by an RC network

with a typical corner frequency of 30 kHz to reduce the effect of

switching noise in the chip supply current generated by the

MOSFET gate driver. The ﬁltered error signal is compared with

the internal oscillator sawtooth waveform to generate the duty

cycle waveform. As the control current increases, the duty cycle

decreases. A clock signal from the oscillator sets a latch that

turns on the output MOSFET. The pulse width modulator resets

the latch, turning off the output MOSFET. Note that a minimum

current must be driven into the CONTROL pin before the duty

cycle begins to change.

V_UV

V_LINE

0 V

S7 S0

S1 S2

5.8 V

4.8 V

V_C

0 V

V_DRAIN

0 V

V_OUT

0 V

Note: S0 through S7 are the output states of the auto-restart counter

PI-3867-050602

Figure 5. Typical Waveforms for (1) Power Up, (2) Normal Operation, (3) Auto-restart and (4) Power Down.

www.powerint.com

Rev. T 12/12

1 2 3 456 7 8...34

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与DPA424SN相关器件

型号	品牌	描述	获取价格	数据表
DPA425	POWERINT	Highly Integrated DC-DC Converter ICs for Distributed Power Architectures	获取价格
DPA425GN	POWERINT	DC-DC Forward Converter Design Guide Application Note AN-31	获取价格
DPA425G-TL	POWERINT	Highly Integrated DC-DC Converter ICs for Distributed Power Architectures	获取价格
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DPA425P-TL	POWERINT	Highly Integrated DC-DC Converter ICs for Distributed Power Architectures	获取价格
DPA425R	POWERINT	Highly Integrated DC-DC Converter ICs for Power over Ethernet & Telecom Applications	获取价格

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