DPA423-426
Pulse Width Modulator and Maximum Duty Cycle
The pulse width modulator implements voltage mode control
by driving the output MOSFET with a duty cycle inversely
proportional to the current into the CONTROL pin that is in
excess of the internal supply current of the chip (see Figure 4).
The excess current is the feedback error signal that appears
acrossRE (seeFigure2).ThissignalisfilteredbyanRCnetwork
with a typical corner frequency of 30 kHz to reduce the effect
of switching noise in the chip supply current generated by the
MOSFETgatedriver.Thefilterederrorsignaliscomparedwith
the internal oscillator sawtooth waveform to generate the duty
cyclewaveform.Asthecontrolcurrentincreases,thedutycycle
decreases. A clock signal from the oscillator sets a latch that
turnsontheoutputMOSFET. Thepulsewidthmodulatorresets
thelatch,turningofftheoutputMOSFET. Notethataminimum
current must be driven into the CONTROL pin before the duty
cycle begins to change.
level. The CONTROL pin current in excess of the supply
current is separated by the shunt regulator and flows through RE
as a voltage error signal.
On-chip Current Limit with External Programmability
The cycle-by-cycle peak drain current limit circuit uses the
output MOSFET ON-resistance as a sense resistor. A current
limit comparator compares the output MOSFET on-state drain
to source voltage, VDS(ON) with a threshold voltage. At the
current limit, VDS(ON) exceeds the threshold voltage and the
MOSFETisturnedoffuntilthestartofthenextclockcycle.The
current limit comparator threshold voltage is temperature
compensated to minimize the variation of the current limit due
totemperaturerelatedchangesinRDS(ON) oftheoutputMOSFET.
The default current limit of DPA-Switch is preset internally.
However, with a resistor connected between EXTERNAL
CURRENT LIMIT pin and SOURCE pin, the current limit can
be programmed externally to a lower level between 25% and
100% of the default current limit. Please refer to the graphs in
the Typical Performance Characteristics section for the
selection of the resistor value. By setting current limit low, a
largerDPA-Switchthannecessaryforthepowerrequiredcanbe
usedtotakeadvantageofthelowerRDS(ON)forhigherefficiency/
smaller heat sinking requirements. With a second resistor
connected between the EXTERNAL CURRENT LIMIT pin
andtheDCinputbus,thecurrentlimitisreducedwithincreasing
line voltage, allowing a true power limiting operation against
line variation to be implemented in a flyback configuration.
The maximum duty cycle, DCMAX is set at a default maximum
value of 75% (typical). However, by connecting the
LINE-SENSE to the DC input bus through a resistor with
appropriate value, the maximum duty cycle can be made to
decrease from 75% to 33% (typical) as shown in
Figure 7 when input line voltage increases (see line feed
forward with DCMAX reduction).
Minimum Duty Cycle and Cycle Skipping
To maintain power supply output regulation, the pulse width
modulator reduces duty cycle as the load at the power supply
output decreases. This reduction in duty cycle is proportional to
the current flowing into the CONTROL pin. As the CONTROL
pin current increases, the duty cycle reduces linearly towards a
minimumvaluespecifiedasminimumdutycycle,DCMIN. After
reaching DCMIN, if CONTROL pin current is increased further
by approximately 2 mA, the pulse width modulator will force
the duty cycle from DCMIN to zero in a discrete step (refer to
Figure 4). This feature allows a power supply to operate in a
cycle skipping mode when the load consumes less power than
the DPA-Switch delivers at minimum duty cycle, DCMIN. No
additional control is needed for the transition between normal
operationandcycleskipping.Astheloadincreasesordecreases,
the power supply automatically switches between normal and
cycle skipping mode as necessary.
The leading edge blanking circuit inhibits the current limit
comparator for a short time after the output MOSFET is turned
on. The leading edge blanking time has been set so that, if a
power supply is designed properly, current spikes caused by
primary-side capacitance and secondary-side rectifier reverse
recovery time should not cause premature termination of the
switching pulse.
The current limit after the leading edge blanking time is as
shown in Figure 31. To avoid triggering the current limit in
normal operation, the drain current waveform should stay
within the envelope shown.
Line Under-Voltage Detection (UV)
At power up, UV keeps DPA-Switch off until the input line
voltage reaches the under voltage upper threshold. At power
down, UV holds DPA-Switch on until the input voltage falls
below the under voltage lower threshold. A single resistor
connected from the LINE-SENSE pin to the DC input bus sets
UV upper and lower thresholds. To avoid false triggering by
noise, a hysteresis is implemented which sets the UV lower
threshold typically at 94% of the UV upper threshold. If the UV
lower threshold is reached during operation without the power
supply losing regulation and the condition stays longer than
10 µs (typical), the device will turn off and stay off until the UV
upper threshold has been reached again. Then, a soft-start
Cycle skipping may be avoided, if so desired, by connecting a
minimum load at the power supply output such that the duty
cycle remains at a level higher than DCMIN at all times.
Error Amplifier
The shunt regulator can also perform the function of an error
amplifier in primary side feedback applications. The shunt
regulator voltage is accurately derived from a temperature-
compensatedbandgapreference.Thegainoftheerroramplifier
is set by the CONTROL pin dynamic impedance. The
CONTROLpinclampsexternalcircuitsignalstotheVC voltage
K
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