DP83TC811-Q1
ZHCST33 –SEPTEMBER 2023
www.ti.com.cn
表6-1. Pin Functions (2) (continued)
PIN
STATE(1)
DESCRIPTION
NAME
NO.
SERIAL MANAGEMENT INTERFACE
Management Data Clock: Synchronous clock to the MDIO serial management input and output data. This clock
may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25 MHz. There is no
minimum clock rate.
MDC
1
I
Management Data Input/Output: Bidirectional management data signal that may be sourced by the management
station or the PHY. This pin requires a pullup resistor.
MDIO
36
OD, IO
Recommended to use a resistor between 2.2 kΩand 9 kΩ.
CONTROL INTERFACE
Interrupt: Active-LOW output, which will be asserted LOW when an interrupt condition occurs. This pin has a weak
internal pullup. Register access is necessary to enable various interrupt triggers. Once an interrupt event flag is set,
register access is required to clear the interrupt event.
INT
2
PU, OD, O
Note: Power-on-RESET (POR) Done interrupt is enabled by default. POR Done interrupt can be cleared by reading
register 节8.6.16.
This pin can be configured as an Active-HIGH output using register 节8.6.9.
Reset: Active-LOW input, which initializes or reinitializes the DP83TC811-Q1. Asserting this pin LOW for at least 1
μs will force a reset process to occur. All internal registers will reinitialize to their default states as specified for
each bit in the 节8.6 section. All bootstrap pins are resampled upon deassertion of reset.
RESET
EN
3
7
PU, I
PD, I
Enable: Active-HIGH input, which will disable the DP83TC811-Q1 when pulled LOW and power down all internal
blocks. Disable state is equivalent to a power-down state.
This pin can be directly tied to VDDIO; enabling the device.
WAKE: Active-HIGH input, which wakes the PHY from SLEEP. Asserting this pin HIGH at power-up will prevent the
PHY from going to SLEEP.
WAKE
INH
8
PD, I
O
This pin can be directly tied to VDDIO to wake the device.
INH: Active-HIGH output, which will be asserted HIGH when the PHY is in SLEEP or DISABLED. This pin is LOW
10
for all other PHY states.
CLOCK INTERFACE
Reference Clock Input (MII / RGMII / SGMII): Reference clock 25-MHz crystal or oscillator input. The device
supports either an external crystal resonator connected across pins XI and XO, or an external CMOS-level oscillator
connected to pin XI only and XO left floating.
XI
5
4
I
Reference Clock Input (RMII): Reference clock 50-MHz CMOS-level oscillator in RMII Slave mode. Reference
clock 25-MHz crystal or oscillator in RMII Master mode.
This is a fail-safe pin. When the PHY is not powered, an external oscillator is allowed to be powered and driving into
this pin. Fail-safe prevents pin back-driving.
Reference Clock Output: XO pin is used for crystal only. This pin should be left floating when a CMOS-level
XO
O
oscillator is connected to XI.
LED/GPIO INTERFACE
LED_0 /
35
S, PD, IO
S, PD, IO
IO
LED_0: Link Status
GPIO_0
LED_1 /
6
LED_1: Link Status and BLINK for TX/RX Activity
Clock Output: 25-MHz reference clock
GPIO_1
CLKOUT /
16
GPIO_2
MEDIUM DEPENDENT INTERFACE
TRD_M
TRD_P
13
12
Differential Transmit and Receive: Bidirectional differential signaling configured for 100BASE-T1 operation, IEEE
IO
802.3bw compliant.
JTAG (IEEE 1149.1)
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: DP83TC811-Q1
English Data Sheet: SNLS742
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