DP83867CS, DP83867IS, DP83867E
ZHCSEC3D –OCTOBER 2015 –REVISED NOVEMBER 2022
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6.1 Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
MAC INTERFACES (SGMII, RGMII)
TRANSMIT DATA Bit 3: This signal carries data from the MAC to the PHY in
RGMII mode. It is synchronous to the transmit clock GTX_CLK.
TX_D3
TX_D2
25
26
I, PD
I, PD
TRANSMIT DATA Bit 2: This signal carries data from the MAC to the PHY in
RGMII mode. It is synchronous to the transmit clock GTX_CLK.
Differential SGMII Data Input: This signal carries data from the MAC to the
PHY in SGMII mode. It is synchronous to the differential SGMII clock input.
This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when
operating in SGMII mode.
SGMII_SIP
TX_D1
27
27
28
I, PD
I, PD
I, PD
TRANSMIT DATA Bit 1: This signal carries data from the MAC to the PHY in
RGMII mode. It is synchronous to the transmit clock GTX_CLK.
Differential SGMII Data Input: This signal carries data from the MAC to the
PHY in SGMII mode. It is synchronous to the differential SGMII clock input.
This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when
operating in SGMII mode.
SGMII_SIN
TRANSMIT DATA Bit 0: This signal carries data from the MAC to the PHY in
RGMII mode. It is synchronous to the transmit clock GTX_CLK.
TX_D0
28
29
I, PD
I, PD
RGMII TRANSMIT CLOCK: This continuous clock signal is sourced from the
MAC layer to the PHY. Nominal frequency is 125 MHz.
GTX_CLK
RGMII RECEIVE CLOCK: Provides the recovered receive clocks for different
modes of operation:
RX_CLK
32
O
2.5 MHz in 10-Mbps mode.
25 MHz in 100-Mbps mode.
125 MHz in 1000-Mbps mode.
Differential SGMII Clock Output: This signal is a continuous 625-MHz clock
signal driven by the PHY in SGMII mode.
This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when
operating in SGMII mode.
SGMII_COP
RX_D0
33
33
34
34
S, O
RECEIVE DATA Bit 0: This signal carries data from the PHY to the MAC in
RGMII mode. It is synchronous to the receive clock RX_CLK.
S, O, PD
S, O, PD
O, PD
Differential SGMII Clock Output: This signal is a continuous 625-MHz clock
signal driven by the MAC in SGMII mode.
This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when
operating in SGMII mode.
SGMII_CON
RX_D1
RECEIVE DATA Bit 1: This signal carries data from the PHY to the MAC in
RGMII mode. It is synchronous to the receive clock RX_CLK.
Differential SGMII Data Output: This signal carries data from the PHY to the
MAC in SGMII mode. It is synchronous to the differential SGMII clock output.
SGMII_SOP
35
S, O, PD
This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when
operating in SGMII mode.
RECEIVE DATA Bit 2: This signal carries data from the PHY to the MAC in
RGMII mode. It is synchronous to the receive clock RX_CLK.
RX_D2
35
36
S, O, PD
S, O, PD
Differential SGMII Data Output: This signal carries data from the PHY to the
MAC in SGMII mode. It is synchronous to the differential SGMII clock output.
This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when
operating in SGMII mode.
SGMII_SON
RECEIVE DATA Bit 3: This signal carries data from the PHY to the MAC in
RGMII mode. It is synchronous to the receive clock RX_CLK.
RX_D3
36
37
O, PD
I, PD
TRANSMIT CONTROL: In RGMII mode, it combines the transmit enable and
the transmit error signals of GMII mode using both clock edges.
TX_CTRL
RECEIVE CONTROL: In RGMII mode, the receive data available and receive
error are combined (RXDV_ER) using both rising and falling edges of the
receive clock (RX_CLK).
RX_CTRL
38
S, O, PD
GENERAL-PURPOSE I/O
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6
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