DP83822HF, DP83822IF, DP83822H, DP83822I
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ZHCSFD6F –JULY 2016 –REVISED JUNE 2021
表6-1. Pin Functions
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
MAC INTERFACE
MII Transmit Clock: MII Transmit Clock provides a 25-MHz reference
clock for 100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps
speed. Note that in MII mode, this clock has constant phase referenced to
the reference clock. Applications requiring such constant phase may use
this feature.
O, Hi-Z
Hi-Z
TX_CLK
2
Unused in RMII Mode
RGMII Transmit Clock: The clock is sourced from the MAC layer to the
PHY. When operating at 100-Mbps speed, this clock must be 25-MHz.
When operating at 10-Mbps speed, this clock must be 2.5-MHz.
Note : When in reset, TX_CLK is an output pin and low value is driven on
it. Only once device is out of reset, TX_CLK is configured as input.
I, PD
Transmit Enable: TX_EN is presented on the rising edge of the TX_CLK.
TX_EN indicates the presence of valid data inputs on TX_D[3:0] in MII
mode and on TX_D[1:0] in RMII mode. TX_EN is an active high signal.
RGMII Transmit Control: TX_CTRL combines transmit enable and
transmit error signals. TX_EN is presented on the rising edge of TX_CLK
and TX_ER on the falling edge of TX_CLK.
TX_EN / TX_CTRL
3
I, PD
I, PD
TX_D0
TX_D1
TX_D2
TX_D3
4
5
6
7
Transmit Data: In MII mode, the transmit data nibble received from the
MAC is synchronous to the rising edge of TX_CLK. In RMII mode,
TX_D[1:0] received from the MAC is synchronous to the rising edge of the
reference clock. In RGMII mode, the transmit data nibble received from
the MAC is synchronous to the rising edge of TX_CLK.
MII Receive Clock: MII Receive Clock provides a 25-MHz reference
clock for 100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps
speed, which is derived from the received data stream.
Unused in RMII Mode
RGMII Receive Clock:RGMII Receive Clock provides a 25-MHz
reference clock for 100-Mbps speed and a 2.5-MHz reference clock for
10-Mbps speed, which is derived from the receive data stream.
RX_CLK
25
26
28
O
Receive Data Valid: This pin indicates valid data is present on the
RX_D[3:0] for MII mode and on RX_D[1:0] in RMII mode, independent
from Carrier Sense.
RGMII Receive Control: RX_CTRL combines receive data valid and
receive error signals. RX_DV is presented on the rising edge of RX_CLK
and RX_ER on the falling edge of RX_CLK.
RX_DV / RX_CTRL
O, S-PD
O, S-PU
Receive Error: This pin indicates that an error symbol has been detected
within a received packet in both MII and RMII mode. In MII mode, RX_ER
is asserted high synchronously to the rising edge of RX_CLK. In RMII
mode, RX_ER is asserted high synchronously to the rising edge of the
reference clock. This pin is not required to be used by the MAC in MII or
RMII because the PHY is corrupting data on a receive error.
Unused in RGMII Mode
RX_ER
RX_D0
RX_D1
RX_D2
30
31
32
Receive Data: Symbols received on the cable are decoded and
presented on these pins synchronous to the rising edge of RX_CLK. They
contain valid data when RX_DV is asserted. A nibble RX_D[3:0] is
received in MII and RGMII modes. 2-bits RX_D[1:0] is received in RMII
Mode. PHY address pins PHY_AD[4:1] are multiplexed with RX_D[3:0],
and are pulled-down. PHY_AD[0] (LSB of the address) is multiplexed with
COL on pin 29, and is pulled up. If no external pullup or pulldown is
present, the default PHY address is 0x01.
O, S-PD
O, S-PU
RX_D3 / GPIO3
1
Carrier Sense: In MII mode this pin is asserted high when the receive or
transmit medium is non-idle.
Carrier Sense / Receive Data Valid: In RMII mode, this pin combines
the RMII Carrier and Receive Data Valid indications.
Unused in RGMII Mode
CRS / CRS_DV
27
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