February 2002
DP83847 DsPHYTER II — Single 10/100 Ethernet Transceiver
General Description
Features
The DP83847 is a full feature single Physical Layer device ■ Low-power 3.3V, 0.18µm CMOS technology
with integrated PMD sublayers to support both 10BASE-T
and 100BASE-TX Ethernet protocols over Category 3 (10
Mb/s) or Category 5 unshielded twisted pair cables.
■ Power consumption < 351mW (typical)
■ 5V tolerant I/Os
■ 5V/3.3V MAC interface
The DP83847 is designed for easy implementation of
■ IEEE 802.3 ENDEC, 10BASE-T transceivers and filters
■ IEEE 802.3u PCS, 100BASE-TX transceivers and filters
■ IEEE 802.3 compliant Auto-Negotiation
10/100 Mb/s Ethernet home or office solutions. It interfaces
to Twisted Pair media via an external transformer. This
device interfaces directly to MAC devices through the IEEE
802.3u standard Media Independent Interface (MII) ensur-
ing interoperability between products from different ven-
dors.
■ Output edge rate control eliminates external filtering for
Transmit outputs
■ BaseLine Wander compensation
The DP83847 utilizes on chip Digital Signal Processing
(DSP) technology and digital Phase Lock Loops (PLLs) for
robust performance under all operating conditions,
enhanced noise immunity, and lower external component
count when compared to analog solutions.
■ IEEE 802.3u MII (16 pins/port)
■ LED support (Link, Rx, Tx, Duplex, Speed, Collision)
■ Single register access for complete PHY status
■ 10/100 Mb/s packet loopback BIST (Built in Self Test)
■ 56-pin LLP package (9w) x (9l) x (.75h) mm
Applications
■ LAN on Motherboard
■ Embedded Applications
System Diagram
DP83847
10/100 Mb/s
10BASE-T
RJ-45
or
Ethernet MAC
DsPHYTER II
MII
100BASE-TX
Status
LEDs
25 MHz
Clock
Typical DsPHYTER II application
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©2002 National Semiconductor Corporation