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DM74LS251MX PDF预览

DM74LS251MX

更新时间: 2024-01-03 05:32:17
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 解复用器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 62K
描述
8-Input Digital Multiplexer

DM74LS251MX 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.150 INCH, MS-012, SOIC-16
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.26
Is Samacsys:N系列:LS
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9 mm逻辑集成电路类型:MULTIPLEXER
最大I(ol):0.024 A功能数量:1
输入次数:8输出次数:1
端子数量:16最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):12 mA
Prop。Delay @ Nom-Sup:28 ns传播延迟(tpd):53 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Multiplexer/Demultiplexers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

DM74LS251MX 数据手册

 浏览型号DM74LS251MX的Datasheet PDF文件第2页浏览型号DM74LS251MX的Datasheet PDF文件第3页浏览型号DM74LS251MX的Datasheet PDF文件第4页浏览型号DM74LS251MX的Datasheet PDF文件第5页浏览型号DM74LS251MX的Datasheet PDF文件第6页 
August 1986  
Revised March 2000  
DM74LS251  
3-STATE 1-of-8 Line Data Selector/Multiplexer  
General Description  
Features  
These data selectors/multiplexers contain full on-chip  
binary decoding to select one-of-eight data sources, and  
feature a strobe-controlled 3-STATE output. The strobe  
must be at a low logic level to enable these devices. The 3-  
STATE outputs permit direct connection to a common bus.  
When the strobe input is HIGH, both outputs are in a high-  
impedance state in which both the upper and lower transis-  
tors of each totem-pole output are OFF, and the output nei-  
ther drives nor loads the bus significantly. When the strobe  
is LOW, the outputs are activated and operate as standard  
TTL totem-pole outputs.  
3-STATE version of DM74LS151  
Interface directly with system bus  
Perform parallel-to-serial conversion  
Permit multiplexing from N-lines to one line  
Complementary outputs provide true and inverted data  
Maximum number of common outputs: 129  
Typical propagation delay time (D to Y): 17 ns  
Typical power dissipation: 35 mW  
To minimize the possibility that two outputs will attempt to  
take a common bus to opposite logic levels, the output con-  
trol circuitry is designed so that the average output disable  
time is shorter than the average output enable time.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS251M  
DM74LS251N  
M16A  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Inputs  
Outputs  
Select  
Strobe  
Y
W
C
X
L
B
X
L
A
X
L
S
H
L
L
L
L
L
L
L
L
Z
Z
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
H = HIGH Logic Level  
L = LOW Logic Level  
X = Don't Care  
Z = High Impedance (OFF)  
D0, D1…D7 = The level of the respective D input  
© 2000 Fairchild Semiconductor Corporation  
DS006415  
www.fairchildsemi.com  

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