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DM74LS256N PDF预览

DM74LS256N

更新时间: 2024-02-27 14:28:42
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 129K
描述
Dual 4-Bit Addressable Latch

DM74LS256N 数据手册

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June 1989  
54LS256/DM74LS256  
Dual 4-Bit Addressable Latch  
General Description  
The ’LS256 is a dual 4-bit addressable latch with common  
control inputs; these include two Address inputs (A0, A1),  
an active LOW enable input (E) and an active LOW Clear  
input (CL). Each latch has a Data input (D) and four outputs  
(Q0Q3).  
could impose a transient wrong address. Therefore, this  
e
CL  
e
should be done only while in the memory mode (E  
HIGH).  
Features  
Y
When the Enable (E) is HIGH and the Clear input (CL) is  
LOW, all outputs (Q0Q3) are LOW. Dual 4-channel demul-  
tiplexing occurs when the CL and E are both LOW. When  
CL is HIGH and E is LOW, the selected output (Q0Q3),  
determined by the Address inputs, follows D. When the E  
goes HIGH, the contents of the latch are stored. When op-  
Serial-to-parallel capability  
Y
Output from each storage bit available  
Y
Random (addressable) data entry  
Y
Easily expandable  
Y
Active low common clear  
e
e
LOW, CL  
erating in the addressable latch mode (E  
HIGH), changing more than one bit of the Address (A0, A1)  
Connection Diagram  
Logic Symbol  
Dual-In-Line Package  
TL/F/9823–1  
TL/F/9823–2  
Order Number 54LS256DMQB,  
54LS256FMQB or DM74LS256N  
See NS Package Number J16A,  
N16E or W16A  
e
e
V
Pin 16  
CC  
GND  
Pin 8  
Pin Names  
A0, A1  
Description  
Common Address Inputs  
Data Inputs  
D , D  
a
b
E
Common Enable Input (Active LOW)  
Conditional Clear Input (Active LOW)  
Side A Latch Outputs  
CL  
Q0 Q a  
3
a
Q0 Q b  
b 3  
Side B Latch Outputs  
C
1995 National Semiconductor Corporation  
TL/F/9823  
RRD-B30M115/Printed in U. S. A.  

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