Datasheet > DG202

DG202

更新时间： 2024-11-25 22:49:03

品牌	Logo	应用领域
英特矽尔 - INTERSIL		开关
页数	文件大小	规格书
7页	74K
描述
Quad SPST, CMOS Analog Switches

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DG202 数据手册

DG201A, DG202

Data Sheet

June 1999

File Number 3117.2

Quad SPST, CMOS Analog Switches

Features

The DG201A and DG202 quad SPST analog switches are

designed using Intersil’s 44V CMOS process. These

bidirectional switches are latch-proof and feature break-

before-make switching. Designed to block signals up to

• Input Signal Range. . . . . . . . . . . . . . . . . . . . . . . . . . ±15V

• Low r (Max). . . . . . . . . . . . . . . . . . . . . . . . . . 175Ω

DS(ON)

• TTL, CMOS Compatible

30V

in the OFF state, the DG201A and DG202 offer the

P-P

• Latch-Up Proof

advantages of low ON resistance (≤175Ω), wide input signal

range (±15V) and provide both TTL and CMOS compatibility.

• True Second Source

• Maximum Supply Ratings. . . . . . . . . . . . . . . . . . . . . . 44V

• Logic Inputs Accept Negative Voltages

The DG201A and DG202 are speciﬁcation and pinout

compatible with the industry standard devices.

Ordering Information

Functional Block Diagrams

DG201A

TEMP.

PKG.

NO.

PART NUMBER RANGE ( C)

PACKAGE

DG201AAK

DG201ABK

DG201ACJ

DG201ACY

DG202AK

DG202CJ

-55 to 125 16 Ld CERDIP

F16.3

-25 to 85

0 to 70

16 Ld CERDIP

16 Ld PDIP

F16.3

E16.3

M16.3

F16.3

E16.3

16 Ld SOIC

-55 to 125 16 Ld CERDIP

0 to 70 16 Ld PDIP

Pinout

DG201A, DG202

(CERDIP, PDIP, SOIC)

TOP VIEW

DG202

V+ (SUB-

V-

STRATE)

GND

SWITCHES SHOWN FOR LOGIC “1” INPUT

TRUTH TABLE

LOGIC

DG201A

DG202

OFF

Logic “0” ≤0.8V, Logic “1” ≥ 2.4V

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

4-1

12 3 4 5 6 7

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与DG202相关器件

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DG202_06	MAXIM	获取价格	Quad SPST CMOS Analog Switches
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DG2026DQ-E3	VISHAY	获取价格	IC DUAL 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, PDSO10, MSOP-10, Multiplexer or Switch
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