Datasheet > DAC1252X_JVC

DAC1252X_JVC

更新时间： 2022-01-19 08:49:00

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
10页	261K
描述
DAC1252X_JVC 2.5V 8BIT 2MSPS DAC DAC1252X_JVC\|Data Sheet

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数据手册

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DAC1252X_JVC 数据手册

DAC1252X_JVC

2.5V 8BIT 2MSPS DAC

TIMING DIAGRAM

00000000

10%

11111111

00000000

DATA

00000000

11111111

90%

VOUT

DATA

50%

VOUT

00000000

11111111

00000000

50%

DATA

0.5LSB

VOUT

50%

Toff

Ton

0.5LSB

VOUT

0.5LSB

0.0V

1. Output delay measured from the 50% point of the rising edge of input data to the full scale transition.

2. Settling time measured from the 50% point of full scale transition to the output remaining within ±1/2 LSB.

3. Output rise/fall time measured between the 10% and 90% points of full scale transition.

FUNCTIONAL DESCRIPTION

1. The DAC1252X_JVC has a 8BIT R-2R block, two decoders, two OP amps, and control block.

2. The digital outputs of two decoders decide the voltage level of R2R block.

^{VRT - VRB}å

Rstring

ⁿ* Dn)

⁽2

2⁸

n =0

3. Normal Conditions : VRT=2.45V , VRB=0.05V, PD=High

You can change the voltages of VRT and VRB to 2.5V and 0.0V , but the performance of DAC1252X_JVC

will be degraded.

SEC ASIC

5 / 10

ANALOG

1 2 3 456 7 8...10

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