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DAC124S085CIMMX PDF预览

DAC124S085CIMMX

更新时间： 2024-02-07 17:37:01
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器数模转换器光电二极管
页数 文件大小 规格书
20页 423K
描述
12-Bit Micro Power QUAD Digital-to-Analog Converter with Rail-to-Rail Output

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DAC124S085CIMMX 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SON包装说明：HVSON, SOLCC10,.11,20
针数：10Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：7 weeks风险等级：5.59
最大模拟输出电压：5.5 V最小模拟输出电压：
转换器类型：D/A CONVERTER输入位码：BINARY
输入格式：SERIALJESD-30 代码：S-PDSO-N10
JESD-609代码：e3长度：3 mm
最大线性误差 (EL)：0.1953%湿度敏感等级：1
位数：12功能数量：1
端子数量：10最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：HVSON封装等效代码：SOLCC10,.11,20
封装形状：SQUARE封装形式：SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：3/5 V
认证状态：Not Qualified座面最大高度：0.8 mm
最大稳定时间：8.5 µs标称安定时间 (tstl)：6 µs
子类别：Other Converters最大压摆率：0.65 mA
标称供电电压：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3 mm
Base Number Matches：1

DAC124S085CIMMX 数据手册

 浏览型号DAC124S085CIMMX的Datasheet PDF文件第3页浏览型号DAC124S085CIMMX的Datasheet PDF文件第4页浏览型号DAC124S085CIMMX的Datasheet PDF文件第5页浏览型号DAC124S085CIMMX的Datasheet PDF文件第7页浏览型号DAC124S085CIMMX的Datasheet PDF文件第8页浏览型号DAC124S085CIMMX的Datasheet PDF文件第9页 
A.C. and Timing Characteristics  
Values shown in this table are design targets and are subject to change before product release.  
The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range  
48 to 4047. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.  
Typical  
(Note 9)  
Limits  
(Note 9)  
Units  
(Limits)  
Symbol  
Parameter  
SCLK Frequency  
Conductions  
fSCLK  
40  
30  
MHz (max)  
400h to C00h code change  
Output Voltage Settling Time  
(Note 10)  
ts  
6
8.5  
µs (max)  
RL = 2kΩ, CL = 200 pF  
SR  
Output Slew Rate  
Glitch Impulse  
1
12  
0.5  
1
V/µs  
nV-sec  
nV-sec  
nV-sec  
nV-sec  
kHz  
Code change from 800h to 7FFh  
Digital Feedthrough  
Digital Crosstalk  
DAC-to-DAC Crosstalk  
Multiplying Bandwidth  
3
VREFIN = 2.5V ± 0.1Vpp  
160  
VREFIN = 2.5V ± 0.1Vpp  
input frequency = 10kHz  
VA = 3V  
Total Harmonic Distortion  
Wake-Up Time  
70  
dB  
0.8  
0.5  
25  
7
µsec  
tWU  
VA = 5V  
µsec  
1/fSCLK  
tCH  
SCLK Cycle Time  
SCLK High time  
SCLK Low Time  
33  
10  
10  
ns (min)  
ns (min)  
ns (min)  
tCL  
7
SYNC Set-up Time prior to SCLK  
Falling Edge  
tSS  
tDS  
tDH  
4
10  
3.5  
3.5  
ns (min)  
ns (min)  
ns (min)  
Data Set-Up Time prior to SCLK  
Falling Edge  
1.5  
1.5  
Data Hold Time after SCLK Falling  
Edge  
tCFSR  
tSYNC  
SCLK fall prior to rise of SYNC  
SYNC High Time  
0
6
3
ns (min)  
ns (min)  
10  
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is  
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed  
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test  
conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.  
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.  
Note 3: When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited to 10 mA. The 20 mA maximum package  
input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.  
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the  
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values  
for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond  
the operating ratings, or the power supply polarity is reversed).  
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.  
Note 6: Reflow temperature profiles are different for lead-free packages.  
Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 5.5V, regardless of VA, will not cause errors in the conversion result. For  
example, if VA is 3V, the digital input pins can be driven with a 5V logic device.  
20173204  
Note 8: To guarantee accuracy, it is required that VA and VREFIN be well bypassed.  
www.national.com  
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