CYWUSB6935
PRELIMINARY
the data as shown in Figure 5-6. In transmit mode, DIO and
DIOVAL are sampled on the falling edge of the IRQ, which
clocks the data as shown in Figure 5-7. The application MCU
samples the DIO and DIOVAL on the rising edge of IRQ.
5.2
DIO Interface
The DIO communications interface is an optional SERDES
bypass data-only transfer interface. In receive mode, DIO and
DIOVAL are valid after the falling edge of IRQ, which clocks
IRQ
DIOVAL
v0
d0
v1
d1
v2
d2
v3
d3
v4
d4
v5
d5
v6
v7
v8
v9
v10
d10
v11
d11
v12
d12
v13
d13
v14
d14
v...
d...
data to mcu
DIO
d6
d7
d8
d9
Figure 5-6. DIO Receive Sequence
IRQ
DIOVAL
DIO
v8
v9
v10
v11
d11
v12
d12
v13
d13
v14
d14
v...
d...
v0
v1
v2
d2
v3
d3
v4
d4
v5
v6
v7
data from mcu
d8
d9
d10
d0
d1
d5
d6
d7
Figure 5-7. DIO Transmit Sequence
interrupt indicates that the oscillator has started, and that the
5.3
Interrupts
device is ready to receive SPI transfers.
The CYWUSB6935 features three sets of interrupts: transmit,
received, and a wake interrupt. These interrupts all share a
single pin (IRQ), but can be independently enabled/disabled.
In transmit mode, all receive interrupts are automatically
disabled, and in transmit mode all receive interrupts are
automatically disabled. However, the contents of the enable
registers are preserved when switching between transmit and
receive modes.
The wake interrupt is enabled by setting bit 0 of the Wake
Enable register (Reg 0x1C, bit 0=1). Whether or not a wake
interrupt is pending is indicated by the state of bit 0 of the Wake
Status register (Reg 0x1D, bit 0). Reading the Wake Status
register (Reg 0x1D) clears the interrupt.
5.3.2
Transmit Interrupts
Interrupts are enabled and the status read through 6 registers:
Receive Interrupt Enable (Reg 0x07), Receive Interrupt Status
(Reg 0x08), Transmit Interrupt Enable (Reg 0x0D), Transmit
Interrupt Status (Reg 0x0E), Wake Enable (Reg 0x1C), Wake
Status (Reg 0x1D).
If more than 1 interrupt is enabled at any time, it is necessary
to read the relevant interrupt status register to determine which
event caused the IRQ pin to assert. Even when a given
interrupt source is disabled, the status of the condition that
would otherwise cause an interrupt can be determined by
reading the appropriate interrupt status register. It is therefore
possible to use the devices without making use of the IRQ pin
at all. Firmware can poll the interrupt status register(s) to wait
for an event, rather than using the IRQ pin.
Four interrupts are provided to flag the occurrence of transmit
events. The interrupts are enabled by writing to the Transmit
Interrupt Enable register (Reg 0x0D), and their status may be
determined by reading the Transmit Interrupt Status register
(Reg 0x0E). If more than 1 interrupt is enabled, it is necessary
to read the Transmit Interrupt Status register (Reg 0x0E) to
determine which event caused the IRQ pin to assert.
The function and operation of these interrupts are described in
detail in Section 7.0.
5.3.3
Receive Interrupts
Eight interrupts are provided to flag the occurrence of receive
events, four each for SERDES A and B. In 64 chips/bit and 32
chips/bit DDR modes, only the SERDES A interrupts are
available, and the SERDES B interrupts will never trigger,
even if enabled. The interrupts are enabled by writing to the
Receive Interrupt Enable register (Reg 0x07), and their status
may be determined by reading the Receive Interrupt Status
register (Reg 0x08). If more than one interrupt is enabled, it is
necessary to read the Receive Interrupt Status register (Reg
0x08) to determine which event caused the IRQ pin to assert.
The polarity of all interrupts can be set by writing to the Config-
uration register (Reg 0x05), and it is possible to configure the
IRQ pin to be open drain (if active low) or open source (if active
high).
5.3.1
Wake Interrupt
When the PD pin is low, the oscillator is stopped. After PD is
deasserted, the oscillator takes time to start, and until it has
done so, it is not safe to use the SPI interface. The wake
The function and operation of these interrupts are described in
detail in Section 7.0.
Document 38-16008 Rev. **
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