CYII5SM1300-EVAL

更新时间： 2024-02-29 08:26:34

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		传感器图像传感器
页数	文件大小	规格书
41页	1703K
描述
1.3 MP CMOS Image Sensor

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技术参数
数据手册

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CYII5SM1300-EVAL 技术参数

生命周期：	Obsolete	Reach Compliance Code：	unknown
风险等级：	5.3	其他特性：	ELECTRONIC SNAPSHOT SHUTTER, ROLLING SHUTTER
阵列类型：	FULL FRAME	主体宽度：	9.29 mm
主体高度：	0.83 mm	主体长度或直径：	10.15 mm
数据速率：	40 Mbps	动态范围：	64 dB
帧速率：	27 fps	水平像素：	1280
外壳：	CERAMIC	主时钟：	40 MHz
安装特点：	SURFACE MOUNT	最大工作电流：	60 mA
最高工作温度：	65 °C	最低工作温度：	-30 °C
光学格式：	2/3 inch	输出接口类型：	I2C INTERFACE
输出范围：	0.50-2.02V	输出类型：	DIGITAL VOLTAGE
封装形状/形式：	RECTANGULAR	像素大小：	6.7X6.7 µm
灵敏度（V / lx.s）：	8.4 V/lx.s	传感器/换能器类型：	IMAGE SENSOR,CMOS
最大供电电压：	4.5 V	最小供电电压：	3 V
表面贴装：	YES	端接类型：	SOLDER
垂直像素：	1024	Base Number Matches：	1

CYII5SM1300-EVAL 数据手册

IBIS5-B-1300 CYII5FM1300AB

X-sequencer. This calibration sequence takes typically 3.5 μs

and is necessary to remove ‘Fixed Pattern Noise’ of the pixels

and of the column amplifiers themselves by means of a double

sampling technique. After the row blanking time, the pixels are

fed to the output amplifier. The pixel rate is equal to the

SYS_CLOCK frequency.

Image Core Operation

Image Core Operation and Signalling

Figure 5 is a functional representation of the image core without

sub-sampling and column/row swapping circuits. Most of the

signals involved are not available from the outside because they

are generated by the X-sequencer and SS-sequencer blocks.

Image Core Supply Considerations

The integration of the pixels is controlled by internal signals such

as reset, sample, and hold which are generated by the on-chip

SS-sequencer that is controlled with the external signals

SS_START and SS_STOP. Reading out the pixel array starts

by applying a Y_START together with a Y_CLOCK signal; inter-

nally this is followed by a calibration sequence to calibrate the

output amplifiers (during the row blanking time). Signals

necessary to do this calibration are generated by the on-chip

The image sensor has several supply voltages:

VDDH is the voltage that controls the sample switches. Do not

apply a higher voltage than this to the chip.

The VDDR_LEFT voltage is the highest (nominal) reset voltage

of the pixel core.

Figure 5. Image Core

Vddreset

VDDR_LEFT

SAMPLE

VDDR_RIGHT

RESET

HOLD

VDDH

Pixel row

Pixel Pixel

Y-left addressing

Y-right addressing

Y_START

Y_CLOCK

Pixel column

Y_START

Y_CLOCK

VDDC

Column amplifiers

Output amplifier

PXL_OUT

Read-pointer

BUS_A

BUS_B

X addressing

SYS_CLOCK

Document #: 38-05710 Rev. *E

Page 5 of 41

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与CYII5SM1300-EVAL相关器件

型号	品牌	描述	获取价格	数据表
CYIIFM1300AB-QDC	CYPRESS	1.3 MP CMOS Image Sensor	获取价格
CYIL1SC1300AA-GAC	CYPRESS	CMOS Sensor, 1280 Horiz pixels, 1024 Vert pixels, 450fps, 5V, Square, Surface Mount, CERAM	获取价格
CYIL1SC1300AA-GSC	CYPRESS	1.3MPxl High Speed CMOS Image Sensor	获取价格
CYIL1SC4000AA-GDC	CYPRESS	4 MegaPixel CMOS Image Sensor	获取价格
CYIL1SE0300AA-QDC	CYPRESS	LUPA-300 CMOS Image Sensor	获取价格
CYIL1SE0300-EVAL	CYPRESS	LUPA-300 CMOS Image Sensor	获取价格

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