IBIS5-B-1300 CYII5FM1300AB
The VDDR_RIGHT voltage is generated from the VDDR_LEFT
voltage using circuit that is programmed with the
Dual Shutter Supply Considerations
a
If you analyze the supply settings listed in Table 3, you can see
some fixed column non-uniformities (FPN) when operating in
rolling shutter mode. If a dual shutter mode (both rolling and
snapshot shutter) is required during operation, you must apply
the supply settings listed in Table 4 to achieve the best possible
image quality.
KNEEPOINT_LSB/MSB bits in the sequencer register (see also
“Pixel reset knee-point for multiple slope operation (bits 8, 9, and
10).” on page 14). You can disconnect the VDDR_RIGHT pin
from the circuit and apply an external voltage to supply the
multiple slope reset voltage by setting the VDDR_RIGHT_EXT
bit in the SEQUENCER register. When no external voltage is
applied (recommended), connect the VDDR_RIGHT pin to a
capacitor (recommended value = 1µF). VDDC is the pixel core
supply. VDDA is the image core and periphery analog supply.
VDDD is the image core and periphery digital supply.
Table 4. Dual Shutter Recommended Supply Settings
Parameter
VDDH
Description
Voltage on HOLD switches.
Highest reset voltage.
Pixel core voltage.
Typ Unit
+4.5
+4.5
+3.0
+3.3
V
V
V
V
Note that the IBIS5-B-1300 image sensor has no on-chip power
rejection circuitry. As a consequence all variations on the analog
supply voltages can contribute to random variations (noise) on
the analog pixel signal, which is seen as random noise in the
image. During the camera design, take precautions to supply the
sensor with very stable supply voltages to avoid this additional
noise. The pixel array (VDDR_LEFT, VDDH and VDDC) analog
supplies are especially vulnerable to this.
VDDR_LEFT
VDDC
VDDA
Analog supply voltage of the
image core.
VDDD
Digital supply voltage of the
image core.
+3.3
V
GNDA
Analog ground.
0
0
0
V
V
V
Snapshot Shutter Supply Considerations
GNDD
Digital ground.
The recommended supply voltage settings listed in Table 3 are
used when the IBIS5-B-1300 sensor is in snapshot shutter mode
only.
GND_AB
Anti-blooming ground.
Image Core Biasing Signals
Table 3. Snapshot Shutter Recommended Supply Settings
Table 5 summarizes the biasing signals required to drive the
IBIS5-A-1300. For optimizations reasons, with respect to speed
and power dissipation of all internal blocks, several biasing
resistors are needed.
Parameter
VDDH
Description
Voltage on HOLD switches.
Highest reset voltage.
Pixel core voltage.
Typ
+4.5
+4.5
+3.3
Unit
V
VDDR_LEFT
VDDC
V
Each biasing signal determines the operation of a corresponding
module in the sense that it controls the speed and power dissi-
pation. The tolerance on the DC-level of the bias levels can vary
±150 mV due to process variations.
V
VDDA
Analog supply voltage of the +3.3
image core.
V
VDDD
Digital supply voltage of the
image core.
+3.3
V
GNDA
Analog ground.
0
0
0
V
V
V
GNDD
Digital ground.
GND_AB
Anti-blooming ground.
Table 5. Overview of Bias Signals
Signal
Comment
Related module
DC-Level
1.0V
DEC_CMD
DAC_VHIGH
DAC_VLOW
AMP_CMD
COL_CMD
PC_CMD
Connect to VDDA with R = 50 kΩ and decouple to GNDA with C = 100 nF. Decoder stage.
Connect to VDDA with R = 0Ω.
Connect to GNDA with R = 0Ω.
High level of DAC.
Low level of DAC.
3.3V
0.0V
Connect to VDDA with R = 50 kΩ and decouple to GNDA with C = 100 nF. Output amplifier stage.
Connect to VDDA with R = 50 kΩ and decouple to GNDA with C = 100 nF. Columns amplifiers stage.
1.2V
1.0V
Connect to VDDA with R = 25 kΩ and decouple to GNDA with C = 100 nF. Pre-charge of column
1.1V
busses.
ADC_CMD
Connect to VDDA with R = 50 kΩ and decouple to GNDA with C = 100 nF. Analog stage of ADC.
Connect to VDDA with R = 360Ω and decouple to GNDA with C = 100 nF. High level of ADC.
Connect to GNDA with R = 1200Ω and decouple to GNDA with C = 100 nF. Low level of ADC.
1.0V
2.7V
1.8V
ADC_VHIGH
ADC_VLOW
Document #: 38-05710 Rev. *C
Page 5 of 40
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