Datasheet > CYII5FM1300AB-SDCES

CYII5FM1300AB-SDCES

更新时间： 2024-02-09 10:38:57

品牌	Logo	应用领域
安森美 - ONSEMI		时钟传感器换能器
页数	文件大小	规格书
42页	1774K
描述
CMOS Image Sensor, IMAGE SENSOR-CMOS, 1280(H) X 1024(V) PIXEL, 27fps, 0.50-2.02V, RECTANGULAR, SURFACE MOUNT, ROHS, CERAMIC, BGA-126

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CYII5FM1300AB-SDCES 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
Reach Compliance Code：	compliant	风险等级：	5.18
其他特性：	ELECTRONIC SNAPSHOT SHUTTER, ROLLING SHUTTER	阵列类型：	FULL FRAME
主体宽度：	9.29 mm	主体高度：	0.83 mm
主体长度或直径：	10.15 mm	数据速率：	40 Mbps
动态范围：	64 dB	帧速率：	27 fps
水平像素：	1280	外壳：	CERAMIC
主时钟：	40 MHz	安装特点：	SURFACE MOUNT
最大工作电流：	60 mA	最高工作温度：	65 °C
最低工作温度：	-30 °C	光学格式：	2/3 inch
输出接口类型：	I2C INTERFACE	输出范围：	0.50-2.02V
输出类型：	DIGITAL VOLTAGE	封装形状/形式：	RECTANGULAR
像素大小：	6.7X6.7 µm	电源：	3.3 V
灵敏度（V / lx.s）：	8.4 V/lx.s	传感器/换能器类型：	IMAGE SENSOR,CMOS
子类别：	CCD Image Sensors	最大供电电压：	4.5 V
最小供电电压：	3 V	表面贴装：	YES
端接类型：	SOLDER	垂直像素：	1024
Base Number Matches：	1

CYII5FM1300AB-SDCES 数据手册

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IBIS5-B-1300

CYII5FM1300AB

Figure 7. Row Structure

Y_SYNC Y_SUB

Y_SWAP12 Y_SWAP30

Reg(n)

DEC(n+1)

Reg(n+1)

Reg(n+2)

Reg(n+3)

Reg(n+4)

SRH

ROW(n+1)

DEC(n+2)

DEC(n+3)

ROW(n+2)

ROW(n+3)

ROW(n+4)

DEC(n+4)

Table 7. Y–Sub-sample Patterns

-correction. There are 2 different offsets that can be adjusted

using the on-chip DAC (7 bit): DAC_FINE and DAC_RAW.

DAC_FINE is used to tune the difference between odd and

even columns; DAC_RAW is used to add a general (both even

and odd columns) to the FPN corrected pixel value. This pixel

value is fed to the first amplifier stage which has an adjustable

gain, controlled by a 4-bit word (“GAIN [0…3]”).

OXOXOXOX

OOXXOOXX

In normal mode the pointer for the pixel row is shifted one at

the time.

When sub-sampling is enabled, Y_SYNC is activated. The

Y-shift register shifts 2 succeeding bits and skips the 2 next

bits. This results in pattern “XXOOXXOO”.

After this, a unity feedback amplifier buffers the signal and the

signal leaves the chip. This 2nd amplifier stage determines the

maximal readout speed, that is, the bandwidth and the slew

rate of the output signal. The whole amplifier chain is designed

for a data rate of 40 Mpix/s (@20 pF).

Activating Y_SWAP12 results in pattern “XOXOXOXO”.

Activating Y_SWAP30 results in pattern “OXOXOXOX”.

Activating both Y_SWAP12 and Y_SWAP30 results in pattern

“OOXXOOXX”.

Output Amplifier Gain Control

The output amplifier gain is controlled by a 4-bit word set in the

AMPLIFIER register (see section “Amplifier Register (6:0)” on

page 15). An overview of the gain settings is given in Table 8.

The addressable pixels range when Y-sub sampling is enabled

is: 0–1, 4–5, 8–9, 12–13, … 1020–1021

Output Amplifier

Table 8. Overview Gain Settings

bits

0000

0001

0010

0011

0100

0101

0110

0111

DC Gain

1.37

bits

1000

1001

1010

1011

1100

1101

1110

1111

DC Gain

6.25

Architecture and Settings

The output amplifier stage is user-programmable for gain and

offset level. Gain is controlled by 4-bit wide word; offset by a

7-bit wide word. Gain settings are on an exponential scale.

Offset is controlled by a 7-bit wide DAC, which selects the

offset voltage between 2 reference voltages (DAC_VHIGH

and DAC_VLOW) on a linear scale.

1.62

7.89

1.96

9.21

2.33

11.00

11.37

11.84

12.32

12.42

2.76

3.50

The amplifier is designed to match the specifications of the

output of the imager array. This signal has a data rate of

40 MHz and is located between 1.17V and 2.95V. The output

impedance of the amplifier is 260Ω.

4.25

5.20

The output signal has a range between 1.17V and 2.95V,

depending on the gain and offset settings of the amplifier. At

unity gain and with a mid-range offset value, the amplifier

outputs a signal in between 1.59V (light) and 2.70V (dark).

This analog range should fit to the input range of the ADC,

external or internal. The output swing in unity gain is approxi-

mately 1.11V and maximum 1.78V at the highest gain settings.

Setting of the DAC Reference Voltage

In the output amplifier, the offset can be trimmed by loading

registers DACRAW_REG and DACFINE_REG. DAC_RAW is

used to adjust the offset of the output amplifier and DAC_FINE

is used to tune the offset between the even and odd columns.

These registers are inputs for 2 DACs (see Figure 9 on page

8) that operate on the same resistor that is connected between

pins DAC_VHIGH and DAC_VLOW. The range of the DAC is

defined using a resistive division with R_VHIGH, R_DACand

Figure 8 on page 8 shows the architecture of the output

amplifier. The odd and even column amplifiers sample both

pixel and reset value to perform a double sampling FPN

R_VLOW

Document #: 38-05710 Rev. *A

Page 7 of 42

1...4 5 678 9 10...42

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