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CY7C4201-15JXCT PDF预览

CY7C4201-15JXCT

更新时间： 2024-02-02 23:18:13
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 先进先出芯片
页数 文件大小 规格书
20页 423K
描述
FIFO, 256X9, 10ns, Synchronous, CMOS, PQCC32, LEAD FREE, PLASTIC, LCC-32

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CY7C4201-15JXCT 技术参数

生命周期：Obsolete零件包装代码：QFJ
包装说明：QCCJ,针数：32
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.48
最长访问时间：10 ns周期时间：15 ns
JESD-30 代码：R-PQCC-J32JESD-609代码：e3
长度：13.97 mm内存密度：2304 bit
内存宽度：9功能数量：1
端子数量：32字数：256 words
字数代码：256工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256X9可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：RECTANGULAR封装形式：CHIP CARRIER
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：3.55 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：MATTE TIN
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD宽度：11.43 mm
Base Number Matches：1

CY7C4201-15JXCT 数据手册

 浏览型号CY7C4201-15JXCT的Datasheet PDF文件第2页浏览型号CY7C4201-15JXCT的Datasheet PDF文件第3页浏览型号CY7C4201-15JXCT的Datasheet PDF文件第4页浏览型号CY7C4201-15JXCT的Datasheet PDF文件第5页浏览型号CY7C4201-15JXCT的Datasheet PDF文件第6页浏览型号CY7C4201-15JXCT的Datasheet PDF文件第7页 
CY7C4421/4201/4211/4221 CY7C4231/4241/425164/256/512/1K/2K/4K/8K  
Synchronous FIFOs  
x 9  
CY7C4421/4201/4211/4221  
CY7C4231/4241/4251  
64/256/512/1K/2K/4K/8K x 9  
Synchronous FIFOs  
■
■
Pin-compatible and functionally equivalent to IDT72421,  
72201, 72211, 72221, 72231, and 72241  
Features  
■
High speed, low power, First-In First-Out (FIFO) memories  
Pb-free Packages Available  
❐
❐
❐
❐
❐
❐
❐
64 × 9 (CY7C4421)  
256 × 9 (CY7C4201)  
512 × 9 (CY7C4211)  
1K × 9 (CY7C4221)  
2K × 9 (CY7C4231)  
4K × 9 (CY7C4241)  
8K × 9 (CY7C4251)  
Functional Description  
The CY7C42X1 are high speed, low power FIFO memories with  
clocked read and write interfaces. All are 9 bits wide. The  
CY7C42X1 are pin-compatible to IDT722X1. Programmable  
features include Almost Full/Almost Empty flags. These FIFOs  
provide solutions for a wide variety of data buffering needs,  
including high speed data acquisition, multiprocessor interfaces,  
and communications buffering.  
■
■
■
■
High speed 100 MHz operation (10 ns read/write cycle time)  
Low power (ICC = 35 mA)  
These FIFOs have 9-bit input and output ports that are controlled  
by separate clock and enable signals. The input port is controlled  
by a free-running clock (WCLK) and two write-enable pins  
(WEN1, WEN2/LD).  
Fully asynchronous and simultaneous read and write operation  
Empty, Full, and Programmable Almost Empty and Almost Full  
status flags  
When WEN1 is LOW and WEN2/LD is HIGH, data is written into  
the FIFO on the rising edge of the WCLK signal. While WEN1,  
WEN2/LD is held active, data is continually written into the FIFO  
on each WCLK cycle. The output port is controlled in a similar  
manner by a free-running read clock (RCLK) and two  
read-enable pins (REN1, REN2). In addition, the CY7C42X1 has  
an output enable pin (OE). The Read (RCLK) and Write (WCLK)  
clocks can be tied together for single-clock operation or the two  
clocks can run independently for asynchronous read/write appli-  
cations. Clock frequencies up to 100 MHz are achievable.  
■
■
■
■
■
■
■
TTL-compatible  
Expandable in width  
Output Enable (OE) pin  
Independent read and write enable pins  
Center power and ground pins for reduced noise  
Width-expansion capability  
Space saving 7 mm × 7 mm 32-pin TQFP  
Depth expansion is possible using one enable input for system  
control, while the other enable is controlled by expansion logic to  
direct the flow of data.  
D
0- 8  
Logic Block Diagram  
INPUT  
REGISTER  
WCLKWEN1 WEN2/LD  
FLAG  
PROGRAM  
REGISTER  
Write  
CONTROL  
EF  
PAE  
PAF  
FF  
FLAG  
LOGIC  
Dual Port  
RAM Array  
64 x 9  
Write  
POINTER  
Read  
POINTER  
8k x 9  
RESET  
LOGIC  
RS  
THREE-STATE  
OUTPUT REGISTER  
Read  
CONTROL  
OE  
Q
0- 8  
RCLK REN1 REN2  
Cypress Semiconductor Corporation  
Document #: 38-06016 Rev. *D  
•
198 Champion Court  
•
San Jose  
,
CA 95134-1709  
•
408-943-2600  
Revised February 4, 2010  
[+] Feedback  
 
 
 
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 		FIFO, 256X9, 20ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
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 		Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

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