CY7C1618KV18/CY7C1620KV18
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
Input Output- Data input output signals: Inputs are sampled on the rising edge of K and K clocks during valid write
Synchronous operations. These pins drive out the requested data when the read operation is active. Valid data is
driven out on the rising edge of both the C and C clocks during read operations or K and K when in single
clock mode. When read access is deselected, Q[x:0] are automatically tristated.
CY7C1618KV18 DQ[17:0]
CY7C1620KV18 DQ[35:0]
LD
Input-
Synchronous load: This input is brought low when a bus cycle sequence is defined. This definition
Synchronous includes address and read and write direction. All transactions operate on a burst of 2 data.
BWS0,
BWS1,
BWS2,
BWS3
Input-
Byte write select (BWS) 0, 1, 2, and 3 Active low: Sampled on the rising edge of the K and K clocks
Synchronous during write operations. Used to select which byte is written into the device during the current portion of
the write operations. Bytes not written remain unaltered.
CY7C1618KV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1620KV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27]
.
All the byte write selects are sampled on the same edge as the data. Deselecting a BWS ignores the
corresponding byte of data and it is not written into the device.
A, A0
Input-
Address inputs: These address inputs are multiplexed for both read and write operations. Internally,
Synchronous the device is organized as 8M × 18 (2 arrays each of 4M × 18) for CY7C1618KV18, and 4M × 36 (2
arrays each of 2M × 36) for CY7C1620KV18.
CY7C1618KV18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 23 address inputs are needed to access the entire memory array.
CY7C1620KV18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 22 address inputs are needed to access the entire memory array. All the address inputs are
ignored when the appropriate port is deselected.
R/W
C
Input-
Synchronous read or write input: When LD is low, this input designates the access type (read when
Synchronous R/W is high, write when R/W is low) for loaded address. R/W must meet the setup and hold times around
edge of K.
Input Clock Positive input clock for output data: C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See application example for further details.
C
Input Clock Negative input clock for output data: C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See application example for further details.
K
Input Clock Positive input clock input: The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
Input Clock Negative input clock input: K is used to capture synchronous data being presented to the device and
K
to drive out data through Q[x:0] when in single clock mode.
CQ
Output Clock CQ referenced with respect to C: This is a free running clock and is synchronized to the input clock
for output data (C) of the DDR II. In the single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in the AC Timing table.
Output Clock CQ referenced with respect to C: This is a free running clock and is synchronized to the input clock
for output data (C) of the DDR II. In the single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in the AC Timing table.
CQ
ZQ
Input
Output impedance matching input: This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
Document Number: 001-44274 Rev. *N
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