Datasheet > CY7B991.5JIT

CY7B991.5JIT

更新时间： 2022-12-28 02:41:09

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
19页	514K
描述
Programmable Skew Clock Buffer

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CY7B991.5JIT 数据手册

CY7B991

CY7B992

Programmable Skew Clock Buffer

Features

Functional Description

■ All output pair skew <100 ps typical (250 maximum)

■ 3.75 to 80 MHz output operation

The CY7B991 and CY7B992 Programmable Skew Clock Buffers

(PSCB) offer user selectable control over system clock functions.

These multiple output clock drivers provide the system integrator

with functions necessary to optimize the timing of high perfor-

mance computer systems. Each of the eight individual drivers,

arranged in four pairs of user controllable outputs, can drive

terminated transmission lines with impedances as low as 50Ω.

They can deliver minimal and specified output skews and full

swing logic levels (CY7B991 TTL or CY7B992 CMOS).

■ User selectable output functions

❐ Selectable skew to 18 ns

❐ Inverted and non-inverted

❐ Operation at 1⁄2 and 1⁄4 input frequency

❐ Operation at 2x and 4x input frequency (input as low as 3.75

MHz)

Each output is hardwired to one of the nine delay or function

configurations. Delay increments of 0.7 to 1.5 ns are determined

by the operating frequency with outputs that skew up to ±6 time

units from their nominal “zero” skew position. The completely

integrated PLL allows cancellation of external load and trans-

mission line delay effects. When this “zero delay” capability of the

PSCB is combined with the selectable output skew functions,

you can create output-to-output delays of up to ±12 time units.

■ Zero input to output delay

■ 50% duty cycle outputs

■ Outputs drive 50Ω terminated lines

■ Low operating current

■ 32-pin PLCC/LCC package

■ Jitter < 200 ps peak-to-peak (< 25 ps RMS)

Divide-by-two and divide-by-four output functions are provided

for additional flexibility in designing complex clock systems.

When combined with the internal PLL, these divide functions

enable distribution of a low frequency clock that are multiplied by

two or four at the clock destination. This facility minimizes clock

distribution difficulty, allowing maximum system clock speed and

flexibility.

Logic Block Diagram

TEST

PHASE

FREQ

DET

VCO AND

TIME UNIT

GENERATOR

FILTER

REF

4Q0

4Q1

4F0

4F1

SELECT

INPUTS

(THREE

LEVEL)

SKEW

3Q0

3F0

3F1

3Q1

SELECT

2Q0

2F0

2F1

MATRIX

2Q1

1Q0

1Q1

1F0

1F1

Cypress Semiconductor Corporation

Document Number: 38-07138 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 22, 2007

12 3 4 5 6 7...19

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