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CY74FCT2374ATQCT PDF预览

CY74FCT2374ATQCT

更新时间: 2024-02-13 07:48:24
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
6页 109K
描述
Bus Driver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 0.150 INCH, QSOP-20

CY74FCT2374ATQCT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QSOP包装说明:SSOP, SSOP20,.25
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.29
系列:FCTJESD-30 代码:R-PDSO-G20
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.012 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE WITH SERIES RESISTOR输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:6.5 ns传播延迟(tpd):6.5 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:FF/Latches最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:3.9 mmBase Number Matches:1

CY74FCT2374ATQCT 数据手册

 浏览型号CY74FCT2374ATQCT的Datasheet PDF文件第2页浏览型号CY74FCT2374ATQCT的Datasheet PDF文件第3页浏览型号CY74FCT2374ATQCT的Datasheet PDF文件第4页浏览型号CY74FCT2374ATQCT的Datasheet PDF文件第5页浏览型号CY74FCT2374ATQCT的Datasheet PDF文件第6页 
1CY74FCT2574T  
fax id: 7028  
CY74FCT2374T  
CY74FCT2574T  
8-Bit Registers  
Features  
Functional Description  
• Function and pinout compatible with FCT and F logic  
• 25output series resistors to reduce transmission line  
reflection noise  
The FCT2374T and FCT2574T are high-speed low-power  
octal D-type flip-flops featuring separate D-type inputs for  
each flip-flop. On-chip termination resistors have been added  
to the outputs to reduce system noise caused by reflections.  
The FCT2374T and FCT2574T can be used to replace the  
FCT374T and FCT574T to reduce noise in an existing design.  
Both devices have three-state outputs for bus oriented appli-  
cations. A buffered clock (CP) and output enable (OE) are  
common to all flip-flops. The FCT2574T is identical to the  
FCT2374T except that all the outputs are on one side of the  
package and inputs on the other side. The flip-flops contained  
in the FCT2374T and FCT2574T will store the state of their  
individual D inputs that meet the set-up and hold time require-  
ments on the LOW-to-HIGH clock (CP) transition. When OE is  
LOW, the contents of the flip-flops are available at the outputs.  
When OE is HIGH, the outputs will be in the high-impedence  
state. The state of output enable does not affect the state of  
the flip-flops.  
• FCT-C speed at 5.2 ns max.  
• Reduced V  
(typically=3.3V) versions of equivalent  
OH  
FCT functions  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
• Power-off disable feature  
• Matched rise and fall times  
• Fully compatible with TTL input and output logic levels  
• ESD > 2000V  
• Sink current  
Source current  
12 mA  
15 mA  
• Edge-triggered D-type inputs  
• 250 MHz typical toggle rate  
• Extended commercial temp. range of –40°C to +85°C  
The outputs are designed with a power-off disable feature to  
allow for live insertion of boards.  
Logic Block Diagram  
Logic Symbol  
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CP  
CP  
D
Q
CP  
D
CP  
D
CP  
D
Q
CP  
D
CP  
D
Q
CP  
D
CP  
D
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CP  
Q
Q
Q
Q
Q
OE  
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
OE  
FCT2374T-5  
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
FCT2374T-6  
Pin Configurations  
SOIC/QSOP  
Top View  
SOIC/QSOP  
Top View  
1
OE  
V
CC  
20  
19  
18  
17  
16  
1
V
20  
OE  
CC  
O
2
O
D
0
0
1
2
3
4
5
6
7
8
9
19  
18  
17  
16  
7
O
0
0
1
O
O
O
O
O
O
3
D
D
1
7
6
D
D
4
D
D
2
2
3
4
FCT2574  
5
O
O
D
D
3
6
5
O
O
1
FCT2374T  
6
D
4
15  
14  
15  
14  
2
7
5
6
7
D
5
D
D
O
5
4
2
8
13  
12  
11  
D
13  
12  
11  
D
6
3
O
9
O
D
7
3
4
CP  
10  
10  
GND  
GND  
CP  
FCT2374T-4  
FCT2374T-2  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
September 1994 – Revised October 1996  

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