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CY74FCT163LDH374APVC PDF预览

CY74FCT163LDH374APVC

更新时间： 2024-02-21 05:52:32
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动光电二极管逻辑集成电路触发器
页数 文件大小 规格书
6页 103K
描述
Bus Driver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.300 INCH, 0.025 INCH PITCH, SSOP-48

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CY74FCT163LDH374APVC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SSOP包装说明：0.300 INCH, 0.025 INCH PITCH, SSOP-48
针数：48Reach Compliance Code：not_compliant
风险等级：5.92其他特性：BUS HOLD I/P'S
系列：FCTJESD-30 代码：R-PDSO-G48
JESD-609代码：e0长度：15.875 mm
负载电容（CL）：30 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.006 A位数：8
功能数量：2端口数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP48,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
电源：3/3.3 VProp。Delay @ Nom-Sup：6.5 ns
传播延迟（tpd）：6.5 ns认证状态：Not Qualified
座面最大高度：2.794 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：7.5 mm
Base Number Matches：1

CY74FCT163LDH374APVC 数据手册

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3H374  
fax id: 7051  
CY74FCT163374  
CY74FCT163H374  
CY74FCT163LD374  
CY74FCT163LDH374  
16-Bit Registers  
CY74FCT163LD2374  
Features  
• Lite Drive™ option for low noise applications  
• 6 mA balanced drive outputs  
• FCT-A speed at 6.5 ns  
• Low power, pin-compatible replacement for LCX, LPT,  
LVC, LVCH & LVT families  
• 5V tolerant inputs and outputs*  
• 6 mA & 24 mA balanced drive outputs  
• Power-off disable outputs permits live insertion  
• Edge-rate control circuitry for reduced noise  
• FCT-C speed at 5.2 ns  
• V = 3.0V to 3.6V  
CC  
• ESD (HBM) > 1100V  
Functional Description  
These devices are 16-bit D-type registers designed for use as  
buffered registers in high-speed, low power bus applications.  
These devices can be used as two independent 8-bit registers  
or as a single 16-bit register by connecting the output Enable  
(OE) and Clock (CLK) inputs. The outputs are 24-mA balanced  
output drivers with current limiting resistors to reduce the need  
for external terminating resistors, and provide for minimal un-  
dershoot and reduced ground bounce. Flow-through pinout  
and small shrink packaging aid in simplifying board layout.  
• Latch-up performance exceeds JEDEC standard no. 17  
• Typical output skew < 250 ps  
• Industrial temperature range of –40°C to +85°C  
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)  
• Typical  
(ground bounce) performance exceeds Mil  
V
olp  
Std 883D  
• V = 2.7V to 3.6V  
CC  
• ESD (HBM) > 2000V  
CY74FCT163H374  
The CY74FCT163H374 and CY74FCT163LDH374 have “bus  
hold” on the data inputs, which retain the input’s last state  
whenever the source driving the input goes to high impedance.  
This eliminates the need for pull-up/down resistors and pre-  
vents floating inputs.  
• Bus hold on data inputs  
• Eliminates the need for external pull-up or pull-down  
resistors  
• *Devices with bus hold are not recommended for trans-  
lating rail-to-rail CMOS signals to 3.3V logic levels  
The CY74FCT163374 and the CY74FCT16LD374 are  
designed with inputs and outputs capable of being driven by  
5.0V buses, allowing them to be used in mixed voltage  
systems as translators. The outputs are also designed with a  
power off disable feature enabling them to be used in  
applications requiring live insertion.  
Logic Block Diagrams CY74FCT163374, CY74FCT163H374,  
CY74FCT163LD374, CY74FCT163LDH374  
Pin Configuration  
SSOP/TSSOP  
Top View  
1
2
3
4
48  
47  
46  
OE  
O
CLK  
1
1
1
D
1
1
1
2
O
D
2
1
1
GND  
O
GND  
D
45  
44  
43  
42  
41  
OE  
OE  
2
1
5
1
1
3
4
1
1
3
4
O
D
6
CLK  
CLK  
2
1
V
CC  
V
CC  
7
O
D
1
1
5
6
1
1
5
6
8
D
C
D
C
D
1
D
1
1
2
O
D
9
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
O
1
O
1
1
2
GND  
GND  
10  
11  
O
D
1
1
7
8
1
1
7
8
O
D
12  
13  
O
O
D
D
2
2
1
2
2
1
14  
15  
16  
17  
18  
2
2
TO 7 OTHER CHANNELS  
TO 7 OTHER CHANNELS  
GND  
GND  
O
D
D
2
3
4
2
3
O
2
2
4
V
CC  
V
CC  
O
5
D
5
19  
20  
21  
22  
23  
24  
30  
29  
28  
27  
26  
25  
2
2
2
2
O
6
D
6
GND  
O
GND  
D
2
2
7
8
2
7
8
O
D
2
2
OE  
CLK  
2
Lite Drive is a trademark of Cypress Semiconductor Corporation.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
March 19, 1997 – Revised April 20, 1998  
123456

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