1CY74FCT162H501
T
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
SCCS057 - August 1994 - Revised March 2000
18-Bit Registered Transceivers
Features
Functional Description
• FCT-E speed at 3.8 ns
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6 mil pitch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of −40˚C to +85˚C
• VCC = 5V ± 10%
These 18-bit universal bus transceivers can be operated in
transparent, latched or clock modes by combining D-type
latches and D-type flip-flops. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CLKAB and CLKBA). For
A-to-B data flow, the device operates in transparent mode
when LEAB is HIGH. When LEAB is LOW, the A data is latched
if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW,
the A bus data is stored in the latch/flip-flop on the
LOW-to-HIGH transition of CLKAB. OEAB performs the output
enable function on the B port. Data flow from B-to-A is similar
to that of A-to-B and is controlled by OEBA, LEBA, and CLKBA.
The output buffers are designed with a power-off disable
feature to allow live insertion of boards.
CY74FCT16501T Features:
• 64 mA sink current, 32 mA source current
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,
TA = 25˚C
The CY74FCT16501T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
THE CY74FCT162501T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for minimal
CY74FCT162501T Features:
• Balanced 24 mA output drivers
• Reduced system switching noise
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,
TA= 25˚C
undershoot
and
reduced
ground
bounce.
The
CY74FCT162501T is ideal for driving transmission lines.
The CY74FCT162H501T is a 24-mA balanced output part, that
has “bus hold” on the data inputs. The device retains the input’s
last state whenever the input goes to high impedance. This
eliminates the need for pull-up/down resistors and prevents
floating inputs.
CY74FCT162H501T Features:
• Bus hold retains last active state
• Eliminates the need for external pull-up or pull-down
resistors
Pin Configuration
SSOP/TSSOP
Functional Block Diagram
Top View
OEAB
LEAB
1
2
56
55
GND
CLKAB
A
1
B
1
GND
3
4
54
53
GND
A
2
B
2
5
6
7
8
9
52
51
50
49
48
OEAB
CLKBA
LEBA
A
B
3
3
V
CC
V
CC
A
4
B
4
A
A
B
5
5
6
B
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEBA
CLKAB
LEAB
GND
GND
A
7
B
7
A
A
B
8
8
9
B
9
A
A
A
B
10
10
C
D
C
D
B
11
B
1
11
12
A
1
B
12
GND
GND
B
13
A
13
C
D
C
D
A
B
14
14
A
B
15
15
V
CC
V
CC
A
A
B
16
16
17
B
17
GND
GND
B
18
FCT16501-1
TO 17 OTHER CHANNELS
A
18
CLKBA
GND
OEBA
LEBA
FCT16501-2
Copyright © 2000, Texas Instruments Incorporated
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