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CY54FCT273TDMB

更新时间： 2024-01-08 18:11:56
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赛普拉斯 - CYPRESS /
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6页 131K
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CY54FCT273TDMB 数据手册

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1CY54/74FCT273T  
fax id: 7025  
CY54/74FCT273T  
8-Bit Register  
Features  
Functional Description  
• Function, pinout, and drive compatible with FCT and  
F logic  
• FCT-C speed at 5.8 ns max. (Com’l)  
FCT-A speed at 7.2 ns max. (Com’l)  
The FCT273T consists of eight edge-triggered D-type  
flip-flops with individual D inputs and Q outputs. The common  
buffered clock (CP) and master reset (MR) load and reset all  
flip-flops simultaneously. The FCT273T is an edge-triggered  
register. The state of each D input (one set-up time before the  
LOW-to-HIGH clock transition) is transferred to the corre-  
sponding flip-flop’s Q output. All outputs will be forced LOW by  
a low voltage level on the MR input.  
• Reduced V  
(typically = 3.3V) versions of equivalent  
OH  
FCT functions  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
• Power-off disable feature  
• Matched rise and fall times  
The outputs are designed with a power-off disable feature to  
allow for live insertion of boards.  
• ESD > 2000V  
• Fully compatible with TTL input and output logic levels  
• Extended commercial range of −40°C to +85°C  
• Sink current  
Source current  
64 mA (Com’l), 32 mA (Mil)  
32 mA (Com’l), 12 mA (Mil)  
Logic Block Diagram  
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CP  
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP  
CP  
CP  
CP  
CP  
CP  
CP  
CP  
R
D
R
D
R
D
R
D
R
D
R
D
R
D
R
D
MR  
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
FCT273T–1  
PinConfigurations  
Logic Symbol  
LCC  
DIP/SOIC/QSOP  
Top View  
Top View  
MR  
1
V
20  
19  
18  
17  
16  
CC  
Q
0
Q
2
7
7
6 5 4  
8
Q
D
0
D
0
D
7
3
3
9
10  
11  
12  
13  
3
2
1
20  
19  
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
GND  
CP  
Q
4
Q
0
MR  
V
CC  
D
1
D
4
6
CP  
Q
1
Q
5
6
MR  
Q
2
Q
5
6
15  
14  
D
4
Q
7
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
D
2
D
5
7
1516 1718  
14  
D
4
D
3
8
13  
12  
11  
Q
3
Q
4
9
FCT273T–4  
GND  
FCT273T–2  
10  
CP  
FCT273T–3  
Function Table[1]  
Inputs  
CP  
Output  
Operating Mode  
Reset (clear)  
Load ‘1’  
MR  
L
D
X
h
l
Q
L
X
H
H
L
Load ‘0’  
H
Note:  
1.  
H
h
L
l
= HIGH Voltage Level steady state  
= HIGH Voltage Level one set-up time prior to LOW-to-HIGH clock transition  
= LOW Voltage Level steady state  
= LOW Voltage Level one set-up time prior to the LOW-to-HIGH transition  
= Don’t Care  
X
= LOW-to-HIGH clock transition  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
March 1995 – Revised March 18, 1997  
123456

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