Datasheet > CS62LS4008FC

CS62LS4008FC

更新时间： 2024-02-24 23:10:10

品牌	Logo	应用领域
其他 - ETC		静态存储器
页数	文件大小	规格书
11页	484K
描述
Low Power CMOS SRAM 512K X 8 Bits

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数据手册

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CS62LS4008FC 数据手册

Low Power CMOS SRAM

512K X 8 Bits

UC62LS4008

-20/-25

WRITE CYCLE2^(1,6)

t_WC

ADDRESS

t_AW

(11)

(2)

t_CW

t_AS

t_WP

t_WHZ

t_OH

D_OUT

(7)

(8)

t_DW

t_DH

D_IN

NOTES:

1. WE\ must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE\ and WE\ low. All signals

must be active to initiate a write and any one can terminate a write by going inactive. The data

input setup and hold timing should be referenced to the second transition edge of the signal that

terminates the write.

3. T_WRis measured from the earlier of CE\ or WE\ going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase to

the outputs must not be applied.

5. If the CE\ low transition occurs simultaneously with the WE\ low transitions or after the WE\

transition, output remain in a high impedance state.

6. OE\ is continuously low (OE\ = V_IL).

7. D_OUTis the same phase of write data of this write cycle.

8. D_OUTis the read data of next address.

9. If CE\ is low during this period, DQ pins are in the output state. Then the data input signals of

opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with C_L= 5pF as shown in Figure 1B. The

parameter is guaranteed but not 100% tested.

11. TCW is measured from the later of CE\ going low to the end of write.

U-Chip Technology Corp. LTD. .

Preliminary Rev.1.0

Reserves the right to modify document contents without notice.

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