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CS4103

更新时间： 2024-01-31 00:10:36

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
24页	402K
描述
IEEE P1394a Physical Layer Device

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CS4103 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	LFQFP, QFP80,.55SQ,20	Reach Compliance Code：	unknown
HTS代码：	8542.31.00.01	风险等级：	5.86
边界扫描：	NO	最大时钟频率：	24.576 MHz
最大数据传输速率：	50 MBps	JESD-30 代码：	S-PQFP-G80
JESD-609代码：	e0	长度：	12 mm
低功率模式：	YES	串行 I/O 数：	3
端子数量：	80	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装等效代码：	QFP80,.55SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
子类别：	Bus Controllers	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	12 mm	uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches：	1

CS4103 数据手册

July 2000

Geode™ CS4103

IEEE P1394a Physical Layer Device

General Description

The National Semiconductor^®Geode™ CS4103 is a three

port 400 Mbit/sec IEEE 1394 Physical Layer (PHY) device.

The CS4103 complies to revision 2.0 of the P1394a specifi-

cation. The device is a three port implementation of a reus-

able cell design scalable from one to sixteen ports.

crystal or a 24.576 MHz clock input. The CS4103 operates

from a single 3.3V supply and supports transfers at 98.304,

196.608, and 393.216 Mbit/sec, (usually referred to as 100,

200, and 400 Mbit/sec respectively).

The CS4103 supports all of the P1394a enhancements

including connection debounce, arbitrated reset, ack-accel-

erated arbitration, fly-by concatenation, multi-speed packet

concatenation, PHY pinging, priority arbitration, and Sus-

pend/Resume operation. It also implements the standard

PHY-Link interface defined in IEEE specification 1394-1995

and updated in the P1394a specification for direct connec-

tion with the Geode CS4210 IEEE 1394 Open Host Con-

troller Interface (OHCI) device. The interface can operate in

either direct or isolated mode and supports single capacitor

isolation with bus hold inputs.

Features

IEEE 1394 Physical Layer Device (PHY) compliant with

revision 2.0 of P1394a including all enhancements

Scalable design from one to sixteen ports

Supports data rates of 100, 200, and 400 Mbit/sec

Single 3.3V supply operation

Internal PLL generates SCLK and all internal clocks

from a single 24.576 MHz crystal or clock

The CS4103 provides a complete PHY solution including

all bias generation, differential line drivers and receivers,

single ended comparators for speed signaling, speed sig-

naling current sources, bias detect, and connect detect cir-

cuitry per port. It includes data and strobe encoding/

decoding functions as well as a re-time FIFO to synchro-

nize the receive data to the local clock domain. The

CS4103 can receive and respond to all the PHY packet

types defined in revision 2.0 of the P1394a specification. It

also supports Suspend and Resume port states and con-

nect detect functions.

Includes Cable Power Sense comparator for cable

power monitoring

Compatible with the Geode CS4210 OHCI Controller

and other IEEE 1394 OHCI devices

Supports the isolated PHY-Link interface compliant with

1394-1995 and P1394a specifications

Single capacitor bus hold isolation\

Power saving modes

80-pin TQFP (Thin Quad Flat Pack)

The CS4103 generates the internal clocks and the Link

SCLK (System Clock) based on a 24.576 MHz external

System Block Diagram

PCI Bus

I C Interface

EEPROM

Geode™ CS4210

IEEE 1394

OHCI Controller

Geode™ CS4103

P1394a

Physical Layer

IEEE 1394

Cable

Connectors

PHY-Link Interface

PCI Interface

National Semiconductor is a registered trademark of National Semiconductor Corporation.

Geode is a trademark of National Semiconductor Corporation.

For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.

www.national.com

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