Datasheet > CR6848

CR6848

更新时间： 2024-01-08 17:27:08

品牌	Logo	应用领域
其他 - ETC		控制器
页数	文件大小	规格书
14页	293K
描述
Novel Low Cost Green-Power PWM Controller

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CR6848 数据手册

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CR6848

Internal

Synchronized

Slop

primary wind inductance. V_INranges from

Compensation

85VAC to 264VAC. To guarantee the output

power is a constant for universal input AC

voltage, there is a dynamic peak limit circuit

to compensate the system delay T that the

system delay brings on.

Although there are more advantages of the

current mode control than conventional

voltage mode control, there are still several

drawbacks of peak-sensing current-mode

converter. Especially the open loop

instability when it operates in higher than

50% of the duty-cycle. CR6848 is introduced

an internal slope compensation adding

voltage ramp to the current sense input

voltage for PWM generation to solve this

problem. It improves the close loop stability

greatly at CCM, prevents the sub-harmonic

oscillation and thus reduces the output

ripple voltage.

Leading-edge Blanking (LEB)

Each time the power MOSFET is switched

on, a turn-on spike will inevitably occur at

the sense pin, which would disturb the

internal signal from the sampling of the

R_SENSE. There is a 300n sec leading edge

blanking time built in to avoid the effect of

the turn-on spike and the power MOSFET

cannot be switched off during this time. So

that the conventional external RC filtering on

sense input is no longer required.

DUTY

V_SLOP= 0.33×

= 0.4389× DUTY

DUTY_MAX

Current Sensing & Dynamic peak

limiting

The current flowing by the power MOSFET

comes in to being a voltage V_SENSEon the

sense pin cycle by cycle, which compares to

the internal reference voltage, controls the

reverse of the internal register, limits the

peak current IMAX of the primary of the

Over Voltage Protection (OVP)

There is a 26.7V over-voltage protection

circuit in the CR6848 to improve the

credibility and extend the life of the chip. The

GATE is to shutdown immediately when the

voltage of the VDD is over 26.7V and the

voltage of VDD is to descend rapidly.

transformer. The energy E = × L× I_MAX

deposited by the transformer. So adjusting

the R_SENSEcan set the Max output power of

the power supple mode. The current flowing

by the power MOSFET has an extra value

Gate Driver & Soft Clamped

CR6848’ output designs a totem pole to

drive a periphery power MOSFET. The dead

time is introduced to minimize the transfixion

current when the output is drove. The

NMOS is shut off when the other NMOS is

turned on. The clamp technology is

introduced to protect the periphery power

MOSFET from breaking down.

V_IN

∆I =

×T_Ddue to the system delay T

L_P

that the current detected from the sense pin

to power MOSFET cut off in the CR6848

(Among these, V_INis the primary winding

voltage of the transformer and L_Pis the

Dec, 2006

V1.5

9/14

Chengdu Chip-Rail Tech.Co.Ltd.

http://www.chiprail.com

1...6 7 8910 11 12...14

中文翻译

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