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CD74HCT147

更新时间: 2024-09-29 23:04:31
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德州仪器 - TI 编码器
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6页 44K
描述
High Speed CMOS Logic 10-to-4 Line Priority Encoder

CD74HCT147 数据手册

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CD74HC147,  
CD74HCT147  
Data sheet acquired from Harris Semiconductor  
SCHS149  
High Speed CMOS Logic  
September 1997  
10-to-4 Line Priority Encoder  
Features  
Description  
[ /Title  
(CD74  
HC147  
,
CD74  
HCT14  
7)  
• Buffered Inputs and Outputs  
The Harris CD74HC147and CD74HCT147 are high speed  
silicon-gate CMOS devices and are pin-compatible with low  
power Schottky TTL (LSTTL).  
• Typical Propagation Delay: 13ns at V  
o
= 5V,  
CC  
C = 15pF, T = 25 C  
L
A
The CD74HC147 and CD74HCT147 9-input priority  
encoders accept data from nine active LOW inputs (l to l )  
and provide binary representation on the four active LOW  
inputs (Y0 to Y3). A priority is assigned to each input so that  
when two or more inputs are simultaneously active, the input  
with the highest priority is represented on the output, with  
• Fanout (Over Temperature Range)  
1
9
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
/Sub-  
ject  
input line l having the highest priority.  
9
(High  
Speed  
CMOS  
Logic  
10-to-4  
Line  
Prior-  
ity  
Encode  
r)  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
These devices provide the 10-line to 4-line priority encoding  
function by use of the implied decimal “zero”. The “zero” is  
encoded when all nine data inputs are HIGH, forcing all four  
outputs HIGH.  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
CC  
Ordering Information  
IL  
IH  
at V  
= 5V  
CC  
PKG.  
• HCT Types  
o
PART NUMBER TEMP. RANGE ( C) PACKAGE  
NO.  
E16.3  
E16.3  
- 4.5V to 5.5V Operation  
CD74HC147E  
CD74HCT147E  
CD74HC147M  
CD74HCT147M  
NOTES:  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
16 Ld PDIP  
16 Ld PDIP  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
/Autho  
r ()  
16 Ld SOIC M16.15  
16 Ld SOIC M16.15  
/Key-  
words  
(High  
Speed  
CMOS  
Logic  
10-to-4  
Line  
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
2. Wafer or die for this part number is available which meets all elec-  
trical specifications. Please contact your local sales office or  
Harris customer service for ordering information.  
Pinout  
Prior-  
ity  
CD74HC147, CD74HCT147  
(PDIP, SOIC)  
Encode  
r, High  
Speed  
CMOS  
Logic  
10-to-4  
Line  
TOP VIEW  
I4  
I5  
1
2
3
4
5
6
7
8
16 V  
CC  
15 NC  
14 Y3  
13 I3  
12 I2  
11 I1  
10 I9  
I6  
I7  
I8  
Y2  
Y1  
GND  
Prior-  
ity  
9
Y0  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1773.1  
Copyright © Harris Corporation 1997  
1

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