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CD74FCT543M96 PDF预览

CD74FCT543M96

更新时间： 2024-02-07 04:20:50
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德州仪器 - TI /
页数 文件大小 规格书
11页 281K
描述
BiCMOS FCT Interface Logic Octal Non-Inverting Registers/Transceivers with 3-State Outputs 24-SOIC 0 to 70

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CD74FCT543M96 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP24,.4针数：24
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.74其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：FCTJESD-30 代码：R-PDSO-G24
长度：15.4 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.064 A位数：8
功能数量：1端口数量：2
端子数量：24最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP24,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 VProp。Delay @ Nom-Sup：8.5 ns
传播延迟（tpd）：12.5 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BICMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：7.5 mm
Base Number Matches：1

CD74FCT543M96 数据手册

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CD74FCT543  
BiCMOS OCTAL REGISTERED TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCBS742 – JULY 2000  
EN, M, OR SM PACKAGE  
(TOP VIEW)  
BiCMOS Technology With Low Quiescent  
Power  
Buffered Inputs  
Inverted Outputs  
LEBA  
OEBA  
A1  
1
2
3
4
5
6
7
8
9
24  
V
CC  
23 CEBA  
22 B1  
Input/Output Isolation From V  
CC  
A2  
A3  
A4  
A5  
A6  
A7  
21 B2  
Controlled Output Edge Rates  
64-mA Output Sink Current  
20 B3  
19 B4  
Output Voltage Swing Limited to 3.7 V  
18 B5  
17 B6  
SCR Latch-Up-Resistant BiCMOS Process  
and Circuit Design  
16 B7  
A8 10  
CEAB 11  
GND 12  
15 B8  
14 LEAB  
13 OEAB  
Package Options Include Plastic  
Small-Outline (M) and Shrink Small-Outline  
(SM) Packages and Standard Plastic (EN)  
DIP  
description  
The CD74FCT543 is an octal register/transceiver with 3-state outputs that uses a small-geometry BiCMOS  
technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level  
to two diode drops below V . This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing  
CC  
[a source of electromagnetic interference (EMI)] and minimizes V  
bounce and ground bounce and their  
CC  
effects during simultaneous output switching. The output configuration also enhances switching speed and is  
capable of sinking 64 mA.  
This device contains two sets of eight D-type latches with separate input and output controls for each set. For  
data flow from A to B, for example, the A-to-B enable (CEAB) input must be low to enter data from A1 to A8 or  
to take data from B1 to B8. When CEAB is low, a low signal on the A-to-B latch enable (LEAB) input makes the  
A-to-B latches transparent; a subsequent low-to-high transition of the LEAB signal puts the A latches in the  
storage mode and their outputs no longer change with the A inputs. With CEABandOEAB both low, the B output  
buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar,  
but uses the CEBA, LEBA, and OEBA inputs.  
The CD74FCT543 contains two sets of D-type latches for temporary storage of data flowing in either direction.  
Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each  
register to permit independent control in either direction of data flow.  
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and  
LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches  
inthestoragemode. WithCEABandOEABbothlow, the3-stateBoutputsareactiveandreflectthedatapresent  
at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and OEBA  
inputs.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The CD74FCT543 is characterized for operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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